ARM64: Question: How to map non-shareable memory

[David Clear]

On Thu, 25 May 2023 at 09:30:27, Catalin Marinas wrote:
> Hi David,

Hi Catalin, thanks for the detailed comments.

I'm finally coming around... The multi-core issues, and having to drop
into kernel mode for the DC IVAC eliminates any possible advantage
this avenue of investigation could have yielded.

> Your best bet is Normal Non-cacheable here.

Yes, we'll stay with Normal_NC. BTW the Cortex A72 issues these as
ReadNoSnoop / WriteNoSnoop, so that's why they made it through the NOC.

> On newer architecture
> versions Arm introduced ST64B/LD64B for similar performance reasons
> (FEAT_LS64 in Armv8.7) but I don't think there's hardware yet.

That's very interesting. Something to look forward to.

Thanks again for your time. Both you and Ard. I appreciate it.

Regards,
David.