ARM64: Question: How to map non-shareable memory

David Clear dclear at amd.com
Wed May 24 14:07:38 PDT 2023


I'd like some advice on how a device driver could map normal, cacheable,
non-shareable memory (currently not supported in the kernel).

I have a device that contains areas of RAM and other internal memories
that are outside of the coherency system, and it's a hardware requirement
in this device that cacheable memory transactions to these areas be
marked as non-shareable.

In practical terms this means that Device or Normal_NC mappings work
today, but Normal (cacheable) mappings will see transaction aborts
(SErrors).

An approach that appears to work is to define a pgprot_nonshared()
macro in arch/arm64/include/asm/pgtable.h which sets the PTE SH bits to
zero, and then define an arm64-specific pgprot_modify() that carries
over the pgprot_nonshared() property, so the PTE changes aren't lost
by vm_pgprot_modify().

That's a bit low-level, so I wonder if there's a better approach. Ideally
I'd like a successful patch to be upstreamed, so I hope there's no
intrinsic resistance to supporting non-shareable mappings.

I'd appreciate your thoughts.

Regards,
David.




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