[PATCH v2 4/6] arm64: zynqmp: Add L2 cache nodes

[Michal Simek]

From: Radhey Shyam Pandey <radhey.shyam.pandey at amd.com>

Describe SoC L2 cache hierarchy.

Signed-off-by: Radhey Shyam Pandey <radhey.shyam.pandey at amd.com>
Signed-off-by: Michal Simek <michal.simek at amd.com>
---

Changes in v2:
- Update commit message to remove Linux part - reported by Laurent

Linux kernel throws "cacheinfo: Unable to detect cache hierarchy for
CPU 0" warning when booting on zu+ Soc. To fix it add the L2 cache
node and let each CPU point to it.

---
 arch/arm64/boot/dts/xilinx/zynqmp.dtsi | 9 +++++++++
 1 file changed, 9 insertions(+)

diff --git a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
index a961bb6f31ff..02bd75900238 100644
--- a/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
+++ b/arch/arm64/boot/dts/xilinx/zynqmp.dtsi
@@ -33,6 +33,7 @@ cpu0: cpu at 0 {
 			operating-points-v2 = <&cpu_opp_table>;
 			reg = <0x0>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu1: cpu at 1 {
@@ -42,6 +43,7 @@ cpu1: cpu at 1 {
 			reg = <0x1>;
 			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu2: cpu at 2 {
@@ -51,6 +53,7 @@ cpu2: cpu at 2 {
 			reg = <0x2>;
 			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
 		};
 
 		cpu3: cpu at 3 {
@@ -60,6 +63,12 @@ cpu3: cpu at 3 {
 			reg = <0x3>;
 			operating-points-v2 = <&cpu_opp_table>;
 			cpu-idle-states = <&CPU_SLEEP_0>;
+			next-level-cache = <&L2>;
+		};
+
+		L2: l2-cache {
+			compatible = "cache";
+			cache-level = <2>;
 		};
 
 		idle-states {
-- 
2.36.1