Excessive TLB flush ranges

[Nadav Amit]

> On May 17, 2023, at 5:12 AM, Russell King (Oracle) <linux at armlinux.org.uk> wrote:
> 
> On Tue, May 16, 2023 at 06:23:27PM -0700, Nadav Amit wrote:
>> Indeed, but ChatGPT says (yes, I see you making fun of me already):
>> “however, this doesn't mean INVLPG has no impact on the pipeline. INVLPG
>> can cause a pipeline stall because the TLB entry invalidation must be
>> completed before subsequent instructions that might rely on the TLB can
>> be executed correctly.”
>> 
>> So I am not sure that your claim is exactly correct.
> 
> Sorry, but chatgpt has no place in serious discussions. You don't know
> where its getting its information from or how reliable it is, and you'll
> only make yourself look silly by quoting it.
> 
> Someone recently asked ChatGPT about me. Apparently I died a few years
> ago. This is news to me. However, this illustrates precisely my point
> that chatgpt can spew utter rubbish that you've no idea where it's got
> it from, and by quoting its output in a serious discussion, you only
> make yourself look silly.

Take it easy Russel, I am not throwing unfiltered stuff. It makes perfect
sense that you get a dependency due to INVLPG with the following load
instructions. Intel SDM does not regard something like that to explicitly
describe when such dependency can occur (flush of the same page or
any page?), but at least in some cases there is no question there is an
impact on the pipeline as otherwise correctness would be violated.

If you have a different experience or think it is nonsensical, let me
know.

Anyhow, I am happy to hear that you didn’t die. :)