[PATCH v14 6/8] arm64: dts: Add AMD Pensando Elba SoC support
Michal Simek
michal.simek at amd.com
Tue May 16 00:54:50 PDT 2023
On 5/15/23 20:16, Brad Larson wrote:
> Add AMD Pensando common and Elba SoC specific device nodes
>
> Signed-off-by: Brad Larson <blarson at amd.com>
> ---
>
> v14 changes:
> - Fix dtbs_check l2-cache* property issue by adding required
> cache-level and cache-unified properties
> - Observed the issue after updating dtschema from 2023.1 to 2023.4
> and yamllint from 1.26.3 to 1.30.0
>
> v11 changes:
> - Delete reset-names
> - Fix spi0 compatible to be specific 'amd,pensando-elba-ctrl'
>
> v9 changes:
> - Single node for spi0 system-controller and squash
> the reset-controller child into parent
>
> ---
> arch/arm64/boot/dts/amd/Makefile | 1 +
> arch/arm64/boot/dts/amd/elba-16core.dtsi | 197 ++++++++++++++++++
> arch/arm64/boot/dts/amd/elba-asic-common.dtsi | 80 +++++++
> arch/arm64/boot/dts/amd/elba-asic.dts | 28 +++
> arch/arm64/boot/dts/amd/elba-flash-parts.dtsi | 106 ++++++++++
> arch/arm64/boot/dts/amd/elba.dtsi | 191 +++++++++++++++++
> 6 files changed, 603 insertions(+)
> create mode 100644 arch/arm64/boot/dts/amd/elba-16core.dtsi
> create mode 100644 arch/arm64/boot/dts/amd/elba-asic-common.dtsi
> create mode 100644 arch/arm64/boot/dts/amd/elba-asic.dts
> create mode 100644 arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
> create mode 100644 arch/arm64/boot/dts/amd/elba.dtsi
>
> diff --git a/arch/arm64/boot/dts/amd/Makefile b/arch/arm64/boot/dts/amd/Makefile
> index 68103a8b0ef5..8502cc2afbc5 100644
> --- a/arch/arm64/boot/dts/amd/Makefile
> +++ b/arch/arm64/boot/dts/amd/Makefile
> @@ -1,2 +1,3 @@
> # SPDX-License-Identifier: GPL-2.0
> +dtb-$(CONFIG_ARCH_PENSANDO) += elba-asic.dtb
> dtb-$(CONFIG_ARCH_SEATTLE) += amd-overdrive-rev-b0.dtb amd-overdrive-rev-b1.dtb
> diff --git a/arch/arm64/boot/dts/amd/elba-16core.dtsi b/arch/arm64/boot/dts/amd/elba-16core.dtsi
> new file mode 100644
> index 000000000000..f9f9f5fd5f69
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amd/elba-16core.dtsi
> @@ -0,0 +1,197 @@
> +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> +/*
> + * Copyright 2020-2022 Advanced Micro Devices, Inc.
2023 and the same below.
> + */
> +
> +/ {
> + cpus {
> + #address-cells = <2>;
> + #size-cells = <0>;
> +
> + cpu-map {
> + cluster0 {
> + core0 { cpu = <&cpu0>; };
> + core1 { cpu = <&cpu1>; };
> + core2 { cpu = <&cpu2>; };
> + core3 { cpu = <&cpu3>; };
> + };
> +
> + cluster1 {
> + core0 { cpu = <&cpu4>; };
> + core1 { cpu = <&cpu5>; };
> + core2 { cpu = <&cpu6>; };
> + core3 { cpu = <&cpu7>; };
> + };
> +
> + cluster2 {
> + core0 { cpu = <&cpu8>; };
> + core1 { cpu = <&cpu9>; };
> + core2 { cpu = <&cpu10>; };
> + core3 { cpu = <&cpu11>; };
> + };
> +
> + cluster3 {
> + core0 { cpu = <&cpu12>; };
> + core1 { cpu = <&cpu13>; };
> + core2 { cpu = <&cpu14>; };
> + core3 { cpu = <&cpu15>; };
> + };
> + };
> +
> + /* CLUSTER 0 */
> + cpu0: cpu at 0 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x0>;
Do you really need 2/0 split here. The first cell is 0 anyway.
> + next-level-cache = <&l2_0>;
> + enable-method = "psci";
> + };
> +
> + cpu1: cpu at 1 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x1>;
> + next-level-cache = <&l2_0>;
> + enable-method = "psci";
> + };
> +
> + cpu2: cpu at 2 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x2>;
> + next-level-cache = <&l2_0>;
> + enable-method = "psci";
> + };
> +
> + cpu3: cpu at 3 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x3>;
> + next-level-cache = <&l2_0>;
> + enable-method = "psci";
> + };
> +
> + l2_0: l2-cache0 {
> + compatible = "cache";
> + cache-unified;
> + cache-level = <2>;
> + };
> +
> + /* CLUSTER 1 */
> + cpu4: cpu at 100 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x100>;
> + next-level-cache = <&l2_1>;
> + enable-method = "psci";
> + };
> +
> + cpu5: cpu at 101 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x101>;
> + next-level-cache = <&l2_1>;
> + enable-method = "psci";
> + };
> +
> + cpu6: cpu at 102 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x102>;
> + next-level-cache = <&l2_1>;
> + enable-method = "psci";
> + };
> +
> + cpu7: cpu at 103 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x103>;
> + next-level-cache = <&l2_1>;
> + enable-method = "psci";
> + };
> +
> + l2_1: l2-cache1 {
> + compatible = "cache";
> + cache-unified;
> + cache-level = <2>;
> + };
> +
> + /* CLUSTER 2 */
> + cpu8: cpu at 200 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x200>;
> + next-level-cache = <&l2_2>;
> + enable-method = "psci";
> + };
> +
> + cpu9: cpu at 201 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x201>;
> + next-level-cache = <&l2_2>;
> + enable-method = "psci";
> + };
> +
> + cpu10: cpu at 202 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x202>;
> + next-level-cache = <&l2_2>;
> + enable-method = "psci";
> + };
> +
> + cpu11: cpu at 203 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x203>;
> + next-level-cache = <&l2_2>;
> + enable-method = "psci";
> + };
> +
> + l2_2: l2-cache2 {
> + compatible = "cache";
> + cache-unified;
> + cache-level = <2>;
> + };
> +
> + /* CLUSTER 3 */
> + cpu12: cpu at 300 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x300>;
> + next-level-cache = <&l2_3>;
> + enable-method = "psci";
> + };
> +
> + cpu13: cpu at 301 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x301>;
> + next-level-cache = <&l2_3>;
> + enable-method = "psci";
> + };
> +
> + cpu14: cpu at 302 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x302>;
> + next-level-cache = <&l2_3>;
> + enable-method = "psci";
> + };
> +
> + cpu15: cpu at 303 {
> + device_type = "cpu";
> + compatible = "arm,cortex-a72";
> + reg = <0 0x303>;
> + next-level-cache = <&l2_3>;
> + enable-method = "psci";
> + };
> +
> + l2_3: l2-cache3 {
> + compatible = "cache";
> + cache-unified;
> + cache-level = <2>;
> + };
> + };
> +};
> diff --git a/arch/arm64/boot/dts/amd/elba-asic-common.dtsi b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi
> new file mode 100644
> index 000000000000..1a615788f54e
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amd/elba-asic-common.dtsi
> @@ -0,0 +1,80 @@
> +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> +/*
> + * Copyright 2020-2022 Advanced Micro Devices, Inc.
> + */
> +
> +&ahb_clk {
> + clock-frequency = <400000000>;
> +};
> +
> +&emmc_clk {
> + clock-frequency = <200000000>;
> +};
> +
> +&flash_clk {
> + clock-frequency = <400000000>;
> +};
> +
> +&ref_clk {
> + clock-frequency = <156250000>;
> +};
> +
> +&qspi {
> + status = "okay";
> +
> + flash0: flash at 0 {
> + compatible = "jedec,spi-nor";
> + reg = <0>;
> + spi-max-frequency = <40000000>;
> + spi-rx-bus-width = <2>;
> + m25p,fast-read;
> + cdns,read-delay = <0>;
> + cdns,tshsl-ns = <0>;
> + cdns,tsd2d-ns = <0>;
> + cdns,tchsh-ns = <0>;
> + cdns,tslch-ns = <0>;
> + };
> +};
> +
> +&gpio0 {
> + status = "okay";
> +};
> +
> +&emmc {
> + bus-width = <8>;
> + cap-mmc-hw-reset;
> + resets = <&rstc 0>;
> + status = "okay";
> +};
> +
> +&wdt0 {
> + status = "okay";
> +};
> +
> +&i2c0 {
> + clock-frequency = <100000>;
> + status = "okay";
> +
> + rtc at 51 {
> + compatible = "nxp,pcf85263";
> + reg = <0x51>;
> + };
> +};
> +
> +&spi0 {
> + #address-cells = <1>;
> + #size-cells = <0>;
> + num-cs = <4>;
> + cs-gpios = <0>, <0>, <&porta 1 GPIO_ACTIVE_LOW>,
> + <&porta 7 GPIO_ACTIVE_LOW>;
> + status = "okay";
> +
> + rstc: system-controller at 0 {
> + compatible = "amd,pensando-elba-ctrl";
> + reg = <0>;
> + spi-max-frequency = <12000000>;
> + interrupt-parent = <&porta>;
> + interrupts = <0 IRQ_TYPE_LEVEL_LOW>;
> + #reset-cells = <1>;
> + };
> +};
> diff --git a/arch/arm64/boot/dts/amd/elba-asic.dts b/arch/arm64/boot/dts/amd/elba-asic.dts
> new file mode 100644
> index 000000000000..c3f4da2f7449
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amd/elba-asic.dts
> @@ -0,0 +1,28 @@
> +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> +/*
> + * Device Tree file for AMD Pensando Elba Board.
> + *
> + * Copyright 2020-2022 Advanced Micro Devices, Inc.
> + */
> +
> +/dts-v1/;
> +
> +#include "elba.dtsi"
> +#include "elba-16core.dtsi"
> +#include "elba-asic-common.dtsi"
> +#include "elba-flash-parts.dtsi"
> +
> +/ {
> + model = "AMD Pensando Elba Board";
> + compatible = "amd,pensando-elba-ortano", "amd,pensando-elba";
> +
> + aliases {
> + serial0 = &uart0;
> + spi0 = &spi0;
> + spi1 = &qspi;
> + };
> +
> + chosen {
> + stdout-path = "serial0:115200n8";
> + };
> +};
> diff --git a/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
> new file mode 100644
> index 000000000000..734893fef2c3
> --- /dev/null
> +++ b/arch/arm64/boot/dts/amd/elba-flash-parts.dtsi
> @@ -0,0 +1,106 @@
> +// SPDX-License-Identifier: (GPL-2.0-only or BSD-2-Clause)
> +/*
> + * Copyright 2020-2022 Advanced Micro Devices, Inc.
> + */
> +
> +&flash0 {
> + partitions {
> + compatible = "fixed-partitions";
> + #address-cells = <1>;
> + #size-cells = <1>;
> + partition at 0 {
> + label = "flash";
> + reg = <0x10000 0xfff0000>;
This doesn't fit with partition at 0 above.
Also size is weird.
> + };
> +
> + partition at f0000 {
> + label = "golduenv";
> + reg = <0xf0000 0x10000>;
> + };
> +
> + partition at 100000 {
> + label = "boot0";
> + reg = <0x100000 0x80000>;
> + };
> +
> + partition at 180000 {
> + label = "golduboot";
> + reg = <0x180000 0x200000>;
> + };
> +
> + partition at 380000 {
> + label = "brdcfg0";
> + reg = <0x380000 0x10000>;
> + };
> +
> + partition at 390000 {
> + label = "brdcfg1";
> + reg = <0x390000 0x10000>;
> + };
> +
> + partition at 400000 {
> + label = "goldfw";
> + reg = <0x400000 0x3c00000>;
This size looks weird.
> + };
> +
> + partition at 4010000 {
> + label = "fwmap";
> + reg = <0x4010000 0x20000>;
> + };
> +
> + partition at 4030000 {
> + label = "fwsel";
> + reg = <0x4030000 0x20000>;
> + };
> +
> + partition at 4090000 {
> + label = "bootlog";
> + reg = <0x4090000 0x20000>;
> + };
> +
> + partition at 40b0000 {
> + label = "panicbuf";
> + reg = <0x40b0000 0x20000>;
> + };
> +
> + partition at 40d0000 {
> + label = "uservars";
> + reg = <0x40d0000 0x20000>;
> + };
> +
> + partition at 4200000 {
> + label = "uboota";
> + reg = <0x4200000 0x400000>;
> + };
> +
> + partition at 4600000 {
> + label = "ubootb";
> + reg = <0x4600000 0x400000>;
> + };
> +
> + partition at 4a00000 {
> + label = "mainfwa";
> + reg = <0x4a00000 0x1000000>;
> + };
> +
> + partition at 5a00000 {
> + label = "mainfwb";
> + reg = <0x5a00000 0x1000000>;
> + };
> +
> + partition at 6a00000 {
> + label = "diaguboot";
> + reg = <0x6a00000 0x400000>;
> + };
> +
here is gap
> + partition at 8000000 {
> + label = "diagfw";
> + reg = <0x8000000 0x7fe0000>;
> + };
> +
> + partition at ffe0000 {
> + label = "ubootenv";
> + reg = <0xffe0000 0x10000>;
> + };
And this is missing space description.
Thanks,
Michal
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