[PATCH v4 00/13] drm/meson: add support for MIPI DSI Display
Neil Armstrong
neil.armstrong at linaro.org
Fri May 12 06:11:31 PDT 2023
The Amlogic G12A, G12B & SM1 SoCs embeds a Synopsys DW-MIPI-DSI transceiver (ver 1.21a),
with a custom glue managing the IP resets, clock and data input similar to the DW-HDMI
glue on the same Amlogic SoCs.
This adds support for the glue managing the transceiver, mimicing the init flow provided
by Amlogic to setup the ENCL encoder, the glue, the transceiver, the digital D-PHY and the
Analog PHY in the proper way.
The DW-MIPI-DSI transceiver + D-PHY are clocked by the GP0 PLL, and the ENCL encoder + VIU
pixel reader by the VCLK2 clock using the HDMI PLL.
The DW-MIPI-DSI transceiver gets this pixel stream as input clocked with the VCLK2 clock.
An optional "MEAS" clock can be enabled to measure the delay between each vsync feeding the
DW-MIPI-DSI transceiver.
This patchset is based on an earlier attempt at [1] for the AXG SoCs, but:
- previous glue code was a single monolitic code mixing encoders & bridges, this version
is aligned on the previous cleanup done on HDMI & CVBS bridges architecture at [2]
- since the only output of AXG is DSI, AXG VPU support is post-poned until we implement
single-clock DSI support specific case on top of this.
This is a re-spin of v3 at [5], the main change is about clock control, the clock
setup has been redesigned to use CCF, a common PLL (GP0) and the VCLK2 clock
path for DSI in preparation of full CCF support and possibly dual display with HDMI.
I kept review tags when the content was only slighly changed.
To: Jerome Brunet <jbrunet at baylibre.com>
To: Michael Turquette <mturquette at baylibre.com>
To: Stephen Boyd <sboyd at kernel.org>
To: Kevin Hilman <khilman at baylibre.com>
To: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
To: Rob Herring <robh+dt at kernel.org>
To: Krzysztof Kozlowski <krzysztof.kozlowski+dt at linaro.org>
To: Conor Dooley <conor+dt at kernel.org>
To: David Airlie <airlied at gmail.com>
To: Daniel Vetter <daniel at ffwll.ch>
To: Philipp Zabel <p.zabel at pengutronix.de>
To: Vinod Koul <vkoul at kernel.org>
To: Kishon Vijay Abraham I <kishon at kernel.org>
To: Sam Ravnborg <sam at ravnborg.org>
Cc: Nicolas Belin <nbelin at baylibre.com>
Cc: linux-amlogic at lists.infradead.org
Cc: linux-clk at vger.kernel.org
Cc: linux-arm-kernel at lists.infradead.org
Cc: linux-kernel at vger.kernel.org
Cc: devicetree at vger.kernel.org
Cc: dri-devel at lists.freedesktop.org
Cc: linux-phy at lists.infradead.org
Signed-off-by: Neil Armstrong <neil.armstrong at linaro.org>
Changes from v3 at [5]:
- switched all clk setup via CCF
- using single PLL for DSI controller & ENCL encoder
- added ENCL clocks to CCF
- make the VCLK2 clocks configuration by CCF
- fixed probe/bind of DSI controller to work with panels & bridges
- added bit_clk to controller to it can setup the BIT clock aswell
- added fix for components unbind
- added fix for analog phy setup value
- added TS050 timings fix
- dropped previous clk control patch
Changes from v2 at [4]:
- Fixed patch 3
- Added reviews from Jagan
- Rebased on v5.19-rc1
Changes from v1 at [3]:
- fixed DSI host bindings
- add reviewed-by tags for bindings
- moved magic values to defines thanks to Martin's searches
- added proper prefixes to defines
- moved phy_configure to phy_init() dw-mipi-dsi callback
- moved phy_on to a new phy_power_on() dw-mipi-dsi callback
- correctly return phy_init/configure errors to callback returns
[1] https://lore.kernel.org/r/20200907081825.1654-1-narmstrong@baylibre.com
[2] https://lore.kernel.org/r/20211020123947.2585572-1-narmstrong@baylibre.com
[3] https://lore.kernel.org/r/20200907081825.1654-1-narmstrong@baylibre.com
[4] https://lore.kernel.org/r/20220120083357.1541262-1-narmstrong@baylibre.com
[5] https://lore.kernel.org/r/20220617072723.1742668-1-narmstrong@baylibre.com
---
Neil Armstrong (13):
dt-bindings: clk: g12a-clkc: export VCLK2_SEL and add CTS_ENCL clock ids
clk: meson: g12a: add CTS_ENCL & CTS_ENCL_SEL clocks
clk: meson: g12a: make VCLK2 and ENCL clock path configurable by CCF
dt-bindings: display: add Amlogic MIPI DSI Host Controller bindings
dt-bindings: display: meson-vpu: add third DPI output port
drm/meson: fix unbind path if HDMI fails to bind
drm/meson: venc: add ENCL encoder setup for MIPI-DSI output
drm/meson: add DSI encoder
drm/meson: add support for MIPI-DSI transceiver
phy: amlogic: phy-meson-g12a-mipi-dphy-analog: fix CNTL2_DIF_TX_CTL0 value
drm/panel: khadas-ts050: update timings to achieve 60Hz refresh rate
arm64: meson: g12-common: add the MIPI DSI nodes
DONOTMERGE: arm64: meson: khadas-vim3l: add DSI panel
.../display/amlogic,meson-g12a-dw-mipi-dsi.yaml | 117 +++++++
.../bindings/display/amlogic,meson-vpu.yaml | 5 +
arch/arm64/boot/dts/amlogic/meson-g12-common.dtsi | 70 ++++
.../boot/dts/amlogic/meson-g12b-khadas-vim3.dtsi | 2 +-
arch/arm64/boot/dts/amlogic/meson-khadas-vim3.dtsi | 76 +++++
.../boot/dts/amlogic/meson-sm1-khadas-vim3l.dts | 2 +-
drivers/clk/meson/g12a.c | 169 +++++++++-
drivers/clk/meson/g12a.h | 3 +-
drivers/gpu/drm/meson/Kconfig | 7 +
drivers/gpu/drm/meson/Makefile | 3 +-
drivers/gpu/drm/meson/meson_drv.c | 32 +-
drivers/gpu/drm/meson/meson_drv.h | 1 +
drivers/gpu/drm/meson/meson_dw_mipi_dsi.c | 364 +++++++++++++++++++++
drivers/gpu/drm/meson/meson_dw_mipi_dsi.h | 160 +++++++++
drivers/gpu/drm/meson/meson_encoder_dsi.c | 174 ++++++++++
drivers/gpu/drm/meson/meson_encoder_dsi.h | 13 +
drivers/gpu/drm/meson/meson_registers.h | 25 ++
drivers/gpu/drm/meson/meson_venc.c | 211 +++++++++++-
drivers/gpu/drm/meson/meson_venc.h | 6 +
drivers/gpu/drm/meson/meson_vpp.h | 2 +
drivers/gpu/drm/panel/panel-khadas-ts050.c | 16 +-
.../phy/amlogic/phy-meson-g12a-mipi-dphy-analog.c | 2 +-
include/dt-bindings/clock/g12a-clkc.h | 3 +
23 files changed, 1428 insertions(+), 35 deletions(-)
---
base-commit: ac9a78681b921877518763ba0e89202254349d1b
change-id: 20230512-amlogic-v6-4-upstream-dsi-ccf-vim3-b8e5217e1f4a
Best regards,
--
Neil Armstrong <neil.armstrong at linaro.org>
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