[QUESTION FOR ARM64 TLB] performance issue and implementation difference of TLB flush

[Gang Li]

Hi,

On 2023/4/28 17:27, Mark Rutland wrote:> The architecture allows a CPU 
to allocate TLB entries at any time for any
> reason, for any valid translation table entries reachable from the 
> root in
> TTBR{0,1}_ELx. That can be due to speculation, prefetching, and/or other
> reasons.
>

TLB will be allocated due to prefetching or branch prediction. Will it
be invalidated when the prediction fails?

> Due to that, it doesn't matter whether or not a CPU explicitly accesses a
> memory location -- TLB entries can be allocated regardless. 
> Consequently, the
> spinlock doesn't make any difference.
>

And is there any kind of ARM manual or guide that
explains these details to help us programming better?

Thanks a lot for your help.
Gang Li