[PATCH v4 17/21] PM / devfreq: rockchip-dfi: account for multiple DDRMON_CTRL registers
Sascha Hauer
s.hauer at pengutronix.de
Fri May 5 04:38:52 PDT 2023
The currently supported RK3399 has a set of registers per channel, but
it has only a single DDRMON_CTRL register. With upcoming RK3588 this
will be different, the RK3588 has a DDRMON_CTRL register per channel.
Instead of expecting a single DDRMON_CTRL register, loop over the
channels and write the channel specific DDRMON_CTRL register. Break
out early out of the loop when there is only a single DDRMON_CTRL
register like on the RK3399.
Signed-off-by: Sascha Hauer <s.hauer at pengutronix.de>
---
drivers/devfreq/event/rockchip-dfi.c | 69 ++++++++++++++++++----------
1 file changed, 46 insertions(+), 23 deletions(-)
diff --git a/drivers/devfreq/event/rockchip-dfi.c b/drivers/devfreq/event/rockchip-dfi.c
index 3d76e58c602b2..74d69153e6386 100644
--- a/drivers/devfreq/event/rockchip-dfi.c
+++ b/drivers/devfreq/event/rockchip-dfi.c
@@ -101,12 +101,13 @@ struct rockchip_dfi {
int burst_len;
int buswidth[DMC_MAX_CHANNELS];
int ddrmon_stride;
+ bool ddrmon_ctrl_single;
};
static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
{
void __iomem *dfi_regs = dfi->regs;
- int ret = 0;
+ int i, ret = 0;
mutex_lock(&dfi->mutex);
@@ -120,28 +121,39 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
goto out;
}
- /* clear DDRMON_CTRL setting */
- writel_relaxed(HIWORD_UPDATE(0, 0xffff), dfi_regs + DDRMON_CTRL);
+ for (i = 0; i < DMC_MAX_CHANNELS; i++) {
+ if (!(dfi->channel_mask & BIT(i)))
+ continue;
- /* set ddr type to dfi */
- switch (dfi->ddr_type) {
- case ROCKCHIP_DDRTYPE_LPDDR2:
- case ROCKCHIP_DDRTYPE_LPDDR3:
- writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23, DDRMON_CTRL_DDR_TYPE_MASK),
- dfi_regs + DDRMON_CTRL);
- break;
- case ROCKCHIP_DDRTYPE_LPDDR4:
- case ROCKCHIP_DDRTYPE_LPDDR4X:
- writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4, DDRMON_CTRL_DDR_TYPE_MASK),
- dfi_regs + DDRMON_CTRL);
- break;
- default:
- break;
- }
+ /* clear DDRMON_CTRL setting */
+ writel_relaxed(HIWORD_UPDATE(0, 0xffff),
+ dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
+
+ /* set ddr type to dfi */
+ switch (dfi->ddr_type) {
+ case ROCKCHIP_DDRTYPE_LPDDR2:
+ case ROCKCHIP_DDRTYPE_LPDDR3:
+ writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR23,
+ DDRMON_CTRL_DDR_TYPE_MASK),
+ dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
+ break;
+ case ROCKCHIP_DDRTYPE_LPDDR4:
+ case ROCKCHIP_DDRTYPE_LPDDR4X:
+ writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_LPDDR4,
+ DDRMON_CTRL_DDR_TYPE_MASK),
+ dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
+ break;
+ default:
+ break;
+ }
+
+ /* enable count, use software mode */
+ writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
+ dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
- /* enable count, use software mode */
- writel_relaxed(HIWORD_UPDATE(DDRMON_CTRL_SOFTWARE_EN, DDRMON_CTRL_SOFTWARE_EN),
- dfi_regs + DDRMON_CTRL);
+ if (dfi->ddrmon_ctrl_single)
+ break;
+ }
out:
mutex_unlock(&dfi->mutex);
@@ -151,6 +163,7 @@ static int rockchip_dfi_enable(struct rockchip_dfi *dfi)
static void rockchip_dfi_disable(struct rockchip_dfi *dfi)
{
void __iomem *dfi_regs = dfi->regs;
+ int i;
mutex_lock(&dfi->mutex);
@@ -161,8 +174,17 @@ static void rockchip_dfi_disable(struct rockchip_dfi *dfi)
if (dfi->usecount > 0)
goto out;
- writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
- dfi_regs + DDRMON_CTRL);
+ for (i = 0; i < DMC_MAX_CHANNELS; i++) {
+ if (!(dfi->channel_mask & BIT(i)))
+ continue;
+
+ writel_relaxed(HIWORD_UPDATE(0, DDRMON_CTRL_SOFTWARE_EN),
+ dfi_regs + i * dfi->ddrmon_stride + DDRMON_CTRL);
+
+ if (dfi->ddrmon_ctrl_single)
+ break;
+ }
+
clk_disable_unprepare(dfi->clk);
out:
mutex_unlock(&dfi->mutex);
@@ -569,6 +591,7 @@ static int rk3399_dfi_init(struct rockchip_dfi *dfi)
dfi->buswidth[1] = FIELD_GET(RK3399_PMUGRF_OS_REG2_BW_CH1, val) == 0 ? 4 : 2;
dfi->ddrmon_stride = 0x14;
+ dfi->ddrmon_ctrl_single = true;
return 0;
};
--
2.39.2
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