[PATCH 0/6] arm64: errata: Disable FWB on parts with non-ARM interconnects

[Rob Herring]

On Thu, Mar 30, 2023 at 11:51 AM James Morse <james.morse at arm.com> wrote:
>
> Hello!
>
> Changes since the RFC?:
>  * Added DT support, in a way that means we don't end up with per-erratum
>    strings, or bloat in the calling code to check for those strings.
>  * Added a commandline argument. (boo)
>  * Changes to support errata affecting features on big-little systems properly.
>
> ~
>
> When stage1 translation is disabled, the SCTRL_E1.I bit controls the
> attributes used for instruction fetch, one of the options results in a
> non-cacheable access. A whole host of CPUs missed the FWB override
> in this case, meaning a KVM guest could fetch stale/junk data instead of
> instructions.
>
> The workaround is to disable FWB, and do the required cache maintenance
> instead.

What's FWB? I don't see it defined anywhere in the series.

Rob