[PATCH v1 05/18] arm64/sysreg: add PIR*_ELx registers

[Catalin Marinas]

On Thu, Mar 16, 2023 at 05:23:48PM +0000, Mark Brown wrote:
> On Thu, Mar 09, 2023 at 02:52:33PM +0000, Joey Gouly wrote:
> 
> > +#define PIE_NONE_O	0x0
> > +#define PIE_R_O		0x1
> > +#define PIE_X_O		0x2
> > +#define PIE_RX_O	0x3
> > +#define PIE_RW_O	0x5
> > +#define PIE_RWnX_O	0x6
> > +#define PIE_RWX_O	0x7
> > +#define PIE_R		0x8
> > +#define PIE_GCS		0x9
> > +#define PIE_RX		0xa
> > +#define PIE_RW		0xc
> > +#define PIE_RWX		0xe
> 
> > +#define PIRx_ELx_PERMIDX(perm, idx)	((perm) << ((idx) * 4))
> 
> This is bikeshedding but every time I look at the uses of this macro I
> find myself trying to read it as index, permission rather than the way
> it is - that's the order for both assignment statements and #defines in
> headers so it's what my brain is reaching for.

You are right, we should probably drop the IDX suffix (or maybe you have
better suggestion for naming it). It refers to the permission field in
the PIR* registers.

-- 
Catalin