[PATCH] dma: ti: k3-udma: Workaround errata i2234

[Jayesh Choudhary]

Hello Peter,

On 10/12/21 20:52, Péter Ujfalusi wrote:
> Hi Vignesh,
> 
> On 09/12/2021 20:07, Vignesh Raghavendra wrote:
>> Per [1], UDMA TR15 transactions may hang if ICNT0 is less than 64B
>> Work around is to set EOL flag is to 1 for ICNT0.
>>
>> Since, there is no performance penalty / side effects of setting EOL
>> flag event ICNTO > 64B, just set the flag for all UDMAP TR15
>> descriptors.
> 
> PDMAs and CSI does not send EOL? If you set it the EOL to one then when
> it arrives the remaining icnt0 is skipped...

I am planning to respin v2 for this.
Will fix this in v2.

> 
>>
>> [1] https://www.ti.com/lit/er/sprz455a/sprz455a.pdf
>> Errata doc for J721E DRA829/TDA4VM Processors Silicon Revision 1.1/1.0 (Rev. A)
>>
>> Signed-off-by: Vignesh Raghavendra <vigneshr at ti.com>
>> ---
>>   drivers/dma/ti/k3-udma.c     | 48 +++++++++++++++++++-----------------
>>   include/linux/dma/ti-cppi5.h |  1 +
>>   2 files changed, 27 insertions(+), 22 deletions(-)
>>

[...]

>> diff --git a/include/linux/dma/ti-cppi5.h b/include/linux/dma/ti-cppi5.h
>> index efa2f0309f00..c53c0f6e3b1a 100644
>> --- a/include/linux/dma/ti-cppi5.h
>> +++ b/include/linux/dma/ti-cppi5.h
>> @@ -616,6 +616,7 @@ static inline void *cppi5_hdesc_get_swdata(struct cppi5_host_desc_t *desc)
>>   #define   CPPI5_TR_CSF_SUPR_EVT			BIT(2)
>>   #define   CPPI5_TR_CSF_EOL_ADV_SHIFT		(4U)
>>   #define   CPPI5_TR_CSF_EOL_ADV_MASK		GENMASK(6, 4)
>> +#define   CPPI5_TR_CSF_EOL_ICNT0		BIT(4)
> 
> the correct expression is: (1 << CPPI5_TR_CSF_EOL_ADV_SHIFT)

Both these expressions expands to the same value
(CPPI5_TR_CSF_EOL_ADV_SHIFT = 4U)

And according to the linux checkpatch, the usage of BIT macro
is preferred so I will keep it the same.

Warm regards,
-Jayesh

> as EOL = 1 is what you want to set.
> EOL = 2 will clear icnt0 and 1 on EOL.
> 3 will do the same for icnt 0, 1 and 2
> 4 will skip the remainin tr.
> 
>>   #define   CPPI5_TR_CSF_EOP			BIT(7)
>>   
>>   /**
>>
>