[PATCH v9 2/5] clk: meson: a1: add Amlogic A1 PLL clock controller driver

[Dmitry Rokosov]

On Mon, Mar 13, 2023 at 10:18:02AM +0100, Jerome Brunet wrote:
> 
> On Thu 09 Mar 2023 at 21:28, Dmitry Rokosov <ddrokosov at sberdevices.ru> wrote:
> 
> >> >> 
> >> >> This last poke should not bits otherwise handled by parms.
> >> >> This is a rate init in disguise.
> >> >> 
> >> >
> >> > I believe, you are talking about hifi_pll clk_regmap conflicts with
> >> > hifi_init_regs. The above init sequence shouldn't affect pll regmap setup,
> >> > it doesn't touch them (we assume that default bit values are all zero):
> >> >
> >> >     .en = {
> >> >         .reg_off = ANACTRL_HIFIPLL_CTRL0,
> >> >         .shift   = 28,
> >> >         .width   = 1,
> >> >     },
> >> >     // init_value = 0x01f18440
> >> >     // en_mask    = 0x10000000
> >> >
> >> >     .m = {
> >> >         .reg_off = ANACTRL_HIFIPLL_CTRL0,
> >> >         .shift   = 0,
> >> >         .width   = 8,
> >> >     },
> >> >     // init_value = 0x01f18440
> >> >     // m_mask     = 0x0000000f
> >> 
> >> mask is 0xff with width 8
> >> 
> >
> > Ah, you're right. Anyway, I think this is just init value and it's okay
> > to set it during initialization and rewrite after in parameter
> > propagation stage.
> >
> 
> ... But the magic pokes are there only to initialize the unmanaged part
> of the clock regs. I'd like it to be clear and stay that way.
> 
> So please, clear the managed fields from the initial poke table.

I've double checked hifi_pll clk. In the my current configuration no any
clks inherited from it. Therefore its 'enable_count' equals to 0.
And of course in the such situation the rate must be zeroed as well.
It means you are right at all. I'll remove pre_sel and fbkdiv hifi_pll
pre-setup in the next version.
Thank you for hunted down!

-- 
Thank you,
Dmitry