[PATCH v5 15/19] clk: mediatek: Add MT8188 vppsys0 clock support
Garmin Chang (張家銘)
Garmin.Chang at mediatek.com
Wed Mar 8 19:23:14 PST 2023
On Fri, 2023-02-03 at 15:33 +0800, Chen-Yu Tsai wrote:
> On Thu, Jan 19, 2023 at 8:54 PM Garmin.Chang <
> Garmin.Chang at mediatek.com> wrote:
> >
> > Add MT8188 vppsys0 clock controller which provides clock gate
> > controller for Video Processor Pipe.
> >
> > Signed-off-by: Garmin.Chang <Garmin.Chang at mediatek.com>
> > ---
> > drivers/clk/mediatek/Makefile | 3 +-
> > drivers/clk/mediatek/clk-mt8188-vpp0.c | 143
> > +++++++++++++++++++++++++
> > 2 files changed, 145 insertions(+), 1 deletion(-)
> > create mode 100644 drivers/clk/mediatek/clk-mt8188-vpp0.c
> >
> > diff --git a/drivers/clk/mediatek/Makefile
> > b/drivers/clk/mediatek/Makefile
> > index 22a3840160fc..48deecc6b520 100644
> > --- a/drivers/clk/mediatek/Makefile
> > +++ b/drivers/clk/mediatek/Makefile
> > @@ -87,7 +87,8 @@ obj-$(CONFIG_COMMON_CLK_MT8188) += clk-mt8188-
> > apmixedsys.o clk-mt8188-topckgen.o
> > clk-mt8188-peri_ao.o clk-mt8188-
> > infra_ao.o \
> > clk-mt8188-cam.o clk-mt8188-
> > ccu.o clk-mt8188-img.o \
> > clk-mt8188-ipe.o clk-mt8188-
> > mfg.o clk-mt8188-vdec.o \
> > - clk-mt8188-vdo0.o clk-mt8188-
> > vdo1.o clk-mt8188-venc.o
> > + clk-mt8188-vdo0.o clk-mt8188-
> > vdo1.o clk-mt8188-venc.o \
> > + clk-mt8188-vpp0.o
> > obj-$(CONFIG_COMMON_CLK_MT8192) += clk-mt8192.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_AUDSYS) += clk-mt8192-aud.o
> > obj-$(CONFIG_COMMON_CLK_MT8192_CAMSYS) += clk-mt8192-cam.o
> > diff --git a/drivers/clk/mediatek/clk-mt8188-vpp0.c
> > b/drivers/clk/mediatek/clk-mt8188-vpp0.c
> > new file mode 100644
> > index 000000000000..e7b46142d653
> > --- /dev/null
> > +++ b/drivers/clk/mediatek/clk-mt8188-vpp0.c
> > @@ -0,0 +1,143 @@
> > +// SPDX-License-Identifier: GPL-2.0-only
> > +//
> > +// Copyright (c) 2022 MediaTek Inc.
> > +// Author: Garmin Chang <garmin.chang at mediatek.com>
> > +
> > +#include <linux/clk-provider.h>
> > +#include <linux/platform_device.h>
> > +#include <dt-bindings/clock/mediatek,mt8188-clk.h>
> > +
> > +#include "clk-gate.h"
> > +#include "clk-mtk.h"
> > +
> > +static const struct mtk_gate_regs vpp0_0_cg_regs = {
> > + .set_ofs = 0x24,
> > + .clr_ofs = 0x28,
> > + .sta_ofs = 0x20,
> > +};
> > +
> > +static const struct mtk_gate_regs vpp0_1_cg_regs = {
> > + .set_ofs = 0x30,
> > + .clr_ofs = 0x34,
> > + .sta_ofs = 0x2c,
> > +};
> > +
> > +static const struct mtk_gate_regs vpp0_2_cg_regs = {
> > + .set_ofs = 0x3c,
> > + .clr_ofs = 0x40,
> > + .sta_ofs = 0x38,
> > +};
> > +
> > +#define GATE_VPP0_0(_id, _name, _parent,
> > _shift) \
> > + GATE_MTK(_id, _name, _parent, &vpp0_0_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +#define GATE_VPP0_1(_id, _name, _parent,
> > _shift) \
> > + GATE_MTK(_id, _name, _parent, &vpp0_1_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +#define GATE_VPP0_2(_id, _name, _parent,
> > _shift) \
> > + GATE_MTK(_id, _name, _parent, &vpp0_2_cg_regs, _shift,
> > &mtk_clk_gate_ops_setclr)
> > +
> > +static const struct mtk_gate vpp0_clks[] = {
> > + /* VPP0_0 */
> > + GATE_VPP0_0(CLK_VPP0_MDP_FG, "vpp0_mdp_fg", "top_vpp", 1),
> > + GATE_VPP0_0(CLK_VPP0_STITCH, "vpp0_stitch", "top_vpp", 2),
> > + GATE_VPP0_0(CLK_VPP0_PADDING, "vpp0_padding", "top_vpp",
> > 7),
> > + GATE_VPP0_0(CLK_VPP0_MDP_TCC, "vpp0_mdp_tcc", "top_vpp",
> > 8),
> > + GATE_VPP0_0(CLK_VPP0_WARP0_ASYNC_TX, "vpp0_warp0_async_tx",
> > "top_vpp", 10),
> > + GATE_VPP0_0(CLK_VPP0_WARP1_ASYNC_TX, "vpp0_warp1_async_tx",
> > "top_vpp", 11),
> > + GATE_VPP0_0(CLK_VPP0_MUTEX, "vpp0_mutex", "top_vpp", 13),
> > + GATE_VPP0_0(CLK_VPP02VPP1_RELAY, "vpp02vpp1_relay",
> > "top_vpp", 14),
> > + GATE_VPP0_0(CLK_VPP0_VPP12VPP0_ASYNC,
> > "vpp0_vpp12vpp0_async", "top_vpp", 15),
> > + GATE_VPP0_0(CLK_VPP0_MMSYSRAM_TOP, "vpp0_mmsysram_top",
> > "top_vpp", 16),
> > + GATE_VPP0_0(CLK_VPP0_MDP_AAL, "vpp0_mdp_aal", "top_vpp",
> > 17),
> > + GATE_VPP0_0(CLK_VPP0_MDP_RSZ, "vpp0_mdp_rsz", "top_vpp",
> > 18),
> > + /* VPP0_1 */
> > + GATE_VPP0_1(CLK_VPP0_SMI_COMMON_MMSRAM,
> > "vpp0_smi_common_mmsram", "top_vpp", 0),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB0_MMSRAM,
> > "vpp0_gals_vdo0_larb0_mmsram", "top_vpp", 1),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_LARB1_MMSRAM,
> > "vpp0_gals_vdo0_larb1_mmsram", "top_vpp", 2),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_MMSRAM,
> > "vpp0_gals_vencsys_mmsram", "top_vpp", 3),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VENCSYS_CORE1_MMSRAM,
> > + "vpp0_gals_vencsys_core1_mmsram", "top_vpp",
> > 4),
> > + GATE_VPP0_1(CLK_VPP0_GALS_INFRA_MMSRAM,
> > "vpp0_gals_infra_mmsram", "top_vpp", 5),
> > + GATE_VPP0_1(CLK_VPP0_GALS_CAMSYS_MMSRAM,
> > "vpp0_gals_camsys_mmsram", "top_vpp", 6),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB5_MMSRAM,
> > "vpp0_gals_vpp1_larb5_mmsram", "top_vpp", 7),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_LARB6_MMSRAM,
> > "vpp0_gals_vpp1_larb6_mmsram", "top_vpp", 8),
> > + GATE_VPP0_1(CLK_VPP0_SMI_REORDER_MMSRAM,
> > "vpp0_smi_reorder_mmsram", "top_vpp", 9),
> > + GATE_VPP0_1(CLK_VPP0_SMI_IOMMU, "vpp0_smi_iommu",
> > "top_vpp", 10),
> > + GATE_VPP0_1(CLK_VPP0_GALS_IMGSYS_CAMSYS,
> > "vpp0_gals_imgsys_camsys", "top_vpp", 11),
> > + GATE_VPP0_1(CLK_VPP0_MDP_RDMA, "vpp0_mdp_rdma", "top_vpp",
> > 12),
> > + GATE_VPP0_1(CLK_VPP0_MDP_WROT, "vpp0_mdp_wrot", "top_vpp",
> > 13),
> > + GATE_VPP0_1(CLK_VPP0_GALS_EMI0_EMI1, "vpp0_gals_emi0_emi1",
> > "top_vpp", 16),
> > + GATE_VPP0_1(CLK_VPP0_SMI_SUB_COMMON_REORDER,
> > "vpp0_smi_sub_common_reorder", "top_vpp", 17),
> > + GATE_VPP0_1(CLK_VPP0_SMI_RSI, "vpp0_smi_rsi", "top_vpp",
> > 18),
> > + GATE_VPP0_1(CLK_VPP0_SMI_COMMON_LARB4,
> > "vpp0_smi_common_larb4", "top_vpp", 19),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VDEC_VDEC_CORE1,
> > "vpp0_gals_vdec_vdec_core1", "top_vpp", 20),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VPP1_WPESYS,
> > "vpp0_gals_vpp1_wpesys", "top_vpp", 21),
> > + GATE_VPP0_1(CLK_VPP0_GALS_VDO0_VDO1_VENCSYS_CORE1,
> > + "vpp0_gals_vdo0_vdo1_vencsys_core1", "top_vpp",
> > 22),
> > + GATE_VPP0_1(CLK_VPP0_FAKE_ENG, "vpp0_fake_eng", "top_vpp",
> > 23),
> > + GATE_VPP0_1(CLK_VPP0_MDP_HDR, "vpp0_mdp_hdr", "top_vpp",
> > 24),
> > + GATE_VPP0_1(CLK_VPP0_MDP_TDSHP, "vpp0_mdp_tdshp",
> > "top_vpp", 25),
> > + GATE_VPP0_1(CLK_VPP0_MDP_COLOR, "vpp0_mdp_color",
> > "top_vpp", 26),
> > + GATE_VPP0_1(CLK_VPP0_MDP_OVL, "vpp0_mdp_ovl", "top_vpp",
> > 27),
> > + GATE_VPP0_1(CLK_VPP0_DSIP_RDMA, "vpp0_dsip_rdma",
> > "top_vpp", 28),
> > + GATE_VPP0_1(CLK_VPP0_DISP_WDMA, "vpp0_disp_wdma",
> > "top_vpp", 29),
> > + GATE_VPP0_1(CLK_VPP0_MDP_HMS, "vpp0_mdp_hms", "top_vpp",
> > 30),
> > + /* VPP0_2 */
> > + GATE_VPP0_2(CLK_VPP0_WARP0_RELAY, "vpp0_warp0_relay",
> > "top_wpe_vpp", 0),
> > + GATE_VPP0_2(CLK_VPP0_WARP0_ASYNC, "vpp0_warp0_async",
> > "top_wpe_vpp", 1),
> > + GATE_VPP0_2(CLK_VPP0_WARP1_RELAY, "vpp0_warp1_relay",
> > "top_wpe_vpp", 2),
> > + GATE_VPP0_2(CLK_VPP0_WARP1_ASYNC, "vpp0_warp1_async",
> > "top_wpe_vpp", 3),
> > +};
> > +
> > +static int clk_mt8188_vpp0_probe(struct platform_device *pdev)
> > +{
> > + struct device *dev = &pdev->dev;
> > + struct device_node *node = dev->parent->of_node;
> > + struct clk_hw_onecell_data *clk_data;
> > + int r;
> > +
> > + clk_data = mtk_alloc_clk_data(CLK_VPP0_NR_CLK);
> > + if (!clk_data)
> > + return -ENOMEM;
> > +
> > + r = mtk_clk_register_gates(node, vpp0_clks,
> > ARRAY_SIZE(vpp0_clks), clk_data);
>
> This API has changed. Please rebase and update.
Thank you for your suggestions.
OK I will modify it in v6.
>
> Otherwise,
>
> Reviewed-by: Chen-Yu Tsai <wenst at chromium.org>
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