[PATCH 0/3] Ampere Computing ETMv4.x Support

[Steve Clevenger]

Hi Suzuki,

To answer your question, Ampere plans to use the existing MMIO
implementation to introduce CoreSight HW Assisted Trace since we're
preparing for release. As a minimum, we know this would require a respin
of our CoreSight DSDT. Also, if I didn't misunderstand, it sounded like
you planned supporting work (e.g. ETMv4 not handled as an AMBA
device). Since our ETMv4 sink components (ETF, ETR, +CATU) remain memory
mapped, do these remain AMBA?

We understand ETMv4/ETE MMIO is going away. As a sysreg quick test, I
bypassed the code which checks for an ETMv4 base address in order to
default to sysreg access. Trace collection failed with an error. I don't
have the time to chase after this right now, but I intend to budget the
time in the near future.

Thanks and regards,
Steve

On 3/6/2023 2:29 AM, Suzuki K Poulose wrote:
> Hi Steve,
> 
> On 06/03/2023 05:54, Steve Clevenger wrote:
>> Ampere ETMv4.x support. Added Ampere ETM ID, and changes required by
>> the Ampere ETMv4.x hardware implementation.
>>
> 
> I don't see any mention of the access via system instructions. Where did
> that end up ? What is the conclusion on that front ?
> 
> Kind regards
> Suzuki
> 
> 
>> Steve Clevenger (3):
>>    Add known list of Ampere ETMv4 errata
>>    coresight etm4x: Early clear TRCOSLAR.OSLK prior to TRCIDR1 read
>>    coresight etm4x: Add 32-bit read/write option to split 64-bit words
>>
>>   Documentation/arm64/silicon-errata.rst        |  6 +-
>>   .../coresight/coresight-etm4x-core.c          | 50 +++++++++++-----
>>   drivers/hwtracing/coresight/coresight-etm4x.h | 58 ++++++++++++++-----
>>   include/linux/coresight.h                     |  3 +
>>   4 files changed, 89 insertions(+), 28 deletions(-)
>>
>