[PATCH 2/3] coresight etm4x: Add 32-bit read/write option to split 64-bit words

[James Clark]

On 20/01/2023 11:19, Suzuki K Poulose wrote:
> On 20/01/2023 00:51, Steve Clevenger wrote:
[...]
>>       }
>> -    for (i = 0; i < drvdata->nr_addr_cmp; i++) {
>> -        etm4x_relaxed_write64(csa, config->addr_val[i], TRCACVRn(i));
>> -        etm4x_relaxed_write64(csa, config->addr_acc[i], TRCACATRn(i));
>> +    for (i = 0; i < drvdata->nr_addr_cmp * 2; i++) {
>> +        if (drvdata->no_quad_mmio) {
>> +            etm4x_split_write64(csa, config->addr_val[i], TRCACVRn(i));
>> +            etm4x_split_write64(csa, config->addr_acc[i], TRCACATRn(i));
>> +        } else {
>> +            etm4x_relaxed_write64(csa, config->addr_val[i],
>> TRCACVRn(i));
>> +            etm4x_relaxed_write64(csa, config->addr_acc[i],
>> TRCACATRn(i));
>> +        }
>> +    }
> 
> Something like this can be leave some places out. I think we could hide
> it under the generic helpers and handle it there. May be "struct
> csdev_access" can cache this "no_quad_mmio" and do the right thing ?

+1 for this, or just pass drvdata to etm4x_relaxed_write64() and then it
can decide what to do. I'd prefer that to caching the value in
csdev_access because it would just be a copy of some other value and
might go stale or not be set at some point.

James