[PATCH v3 1/1] net: axienet: Move reset before DMA detection

[Pandey, Radhey Shyam]

> -----Original Message-----
> From: Maxim Kochetkov <fido_max at inbox.ru>
> Sent: Friday, June 23, 2023 12:22 AM
> To: netdev at vger.kernel.org
> Cc: Maxim Kochetkov <fido_max at inbox.ru>; Robert Hancock
> <robert.hancock at calian.com>; Pandey, Radhey Shyam
> <radhey.shyam.pandey at amd.com>; David S. Miller
> <davem at davemloft.net>; Eric Dumazet <edumazet at google.com>; Jakub
> Kicinski <kuba at kernel.org>; Paolo Abeni <pabeni at redhat.com>; Simek,
> Michal <michal.simek at amd.com>; Andre Przywara
> <andre.przywara at arm.com>; linux-arm-kernel at lists.infradead.org; linux-
> kernel at vger.kernel.org
> Subject: [PATCH v3 1/1] net: axienet: Move reset before DMA detection
> 
> DMA detection will fail if axienet was started before (by boot loader,
> boot ROM, etc). In this state axienet will not start properly.
> XAXIDMA_TX_CDESC_OFFSET + 4 register (MM2S_CURDESC_MSB) is used to
> detect
> 64 DMA capability here. But datasheet says: When DMACR.RS is 1
> (axienet is in enabled state), CURDESC_PTR becomes Read Only (RO) and
> is used to fetch the first descriptor. So iowrite32()/ioread32() trick
> to this register to detect DMA will not work.
> So move axienet reset before DMA detection.
> 
> Fixes: f735c40ed93c ("net: axienet: Autodetect 64-bit DMA capability")
> Signed-off-by: Maxim Kochetkov <fido_max at inbox.ru>
> Reviewed-by: Robert Hancock <robert.hancock at calian.com>

Reviewed-by: Radhey Shyam Pandey <radhey.shyam.pandey at amd.com>
Thanks!
> ---
>  drivers/net/ethernet/xilinx/xilinx_axienet_main.c | 10 +++++-----
>  1 file changed, 5 insertions(+), 5 deletions(-)
> 
> diff --git a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> index 3e310b55bce2..734822321e0a 100644
> --- a/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> +++ b/drivers/net/ethernet/xilinx/xilinx_axienet_main.c
> @@ -2042,6 +2042,11 @@ static int axienet_probe(struct platform_device
> *pdev)
>  		goto cleanup_clk;
>  	}
> 
> +	/* Reset core now that clocks are enabled, prior to accessing MDIO
> */
> +	ret = __axienet_device_reset(lp);
> +	if (ret)
> +		goto cleanup_clk;
> +
>  	/* Autodetect the need for 64-bit DMA pointers.
>  	 * When the IP is configured for a bus width bigger than 32 bits,
>  	 * writing the MSB registers is mandatory, even if they are all 0.
> @@ -2096,11 +2101,6 @@ static int axienet_probe(struct platform_device
> *pdev)
>  	lp->coalesce_count_tx = XAXIDMA_DFT_TX_THRESHOLD;
>  	lp->coalesce_usec_tx = XAXIDMA_DFT_TX_USEC;
> 
> -	/* Reset core now that clocks are enabled, prior to accessing MDIO
> */
> -	ret = __axienet_device_reset(lp);
> -	if (ret)
> -		goto cleanup_clk;
> -
>  	ret = axienet_mdio_setup(lp);
>  	if (ret)
>  		dev_warn(&pdev->dev,
> --
> 2.40.1