[PATCH v2] PCI: imx6: Save and restore MSI control of RC in suspend and resume

[Lorenzo Pieralisi]

On Mon, Apr 10, 2023 at 06:48:48AM +0000, Hongxing Zhu wrote:

[...]

> > I am getting back to this since I am still not convinced and I want to understand
> > this once for all.
> > 
> > We do use dw_pcie_find_capability() in most DWC drivers to find and peek/poke
> > at eg PCI express capability of the *Root port* (?),
> > 
> > eg dw_pcie_wait_for_link()
> > 
> > so I assume that for iMX6 dw_pcie_find_capability() does just the same, which
> > would mean that we are poking the "Message Control" field of the Root port MSI
> > capability.
> > 
> > Either that (which would mean that iMX6 has a HW bug because the RP Message
> > Control field does not control the delivery of MSIs from endpoints but just for the
> > root port itself ) or all DWC controllers modelled the root complex MMIO space as
> > a set of PCI/PCIe capabilities that are NOT necessarily mappable to PCI
> > specifications defined ones.
> > 
> > Can anyone please shed some light on this ? I don't have DWC HW, we need to
> > know before merging this code.
> Hi Lorenzo:
> Regarding my understanding, DWC HW has the PCI/PCIe capability map when
>  it works in RC mode and Spec doesn’t specify these Caps for host controller.
> And, there are comments describe these callbacks already in pcie-designware.c.
> ...
> /*
>  * These interfaces resemble the pci_find_*capability() interfaces, but these
>  * are for configuring host controllers, which are bridges *to* PCI devices but
>  * are not PCI devices themselves.
>  */
> static u8 __dw_pcie_find_next_cap(struct dw_pcie *pci, u8 cap_ptr,
>                                   u8 cap)
> ...
> 
> 

I still believe this is an integration bug, more so after reading the
commit Serge pointed out:

75cb8d20c112 ("PCI: imx: Enable MSI from downstream components").

The commit above implies that if you have CONFIG_PCIEPORTBUS enabled,
you would not need to set the MSI enable bit explicitly because that's
done by the port driver while requesting RP services.

This means that it is _seen_ by the PCI core as a capability register
and it also means that if you have CONFIG_PCIEPORTBUS enabled and that
the port driver disables MSIs, all downstream MSIs are disabled, not
only the RP ones (as it should be according to the PCI specs).

So, this is a HW bug I am afraid - I will merge this patch but AFAICS
the HW integration bug is there regardless, however we slice it.

Thanks,
Lorenzo