[PATCH 3/6] clk: meson: t7: add peripheral clock controller

[kernel test robot]

Hi Lucas,

kernel test robot noticed the following build warnings:

[auto build test WARNING on robh/for-next]
[also build test WARNING on clk/clk-next tty/tty-testing tty/tty-next tty/tty-linus krzk/for-next krzk-dt/for-next krzk-mem-ctrl/for-next linus/master v6.4-rc6 next-20230616]
[If your patch is applied to the wrong git tree, kindly drop us a note.
And when submitting patch, we suggest to use '--base' as documented in
https://git-scm.com/docs/git-format-patch#_base_tree_information]

url:    https://github.com/intel-lab-lkp/linux/commits/Lucas-Tanure/dt-bindings-arm-amlogic-add-Amlogic-T7-based-Khadas-VIM4-bindings/20230616-023038
base:   https://git.kernel.org/pub/scm/linux/kernel/git/robh/linux.git for-next
patch link:    https://lore.kernel.org/r/20230615182938.18487-4-tanure%40linux.com
patch subject: [PATCH 3/6] clk: meson: t7: add peripheral clock controller
config: arm64-buildonly-randconfig-r004-20230615 (https://download.01.org/0day-ci/archive/20230616/202306161946.Kk7xeos8-lkp@intel.com/config)
compiler: aarch64-linux-gcc (GCC) 12.3.0
reproduce: (https://download.01.org/0day-ci/archive/20230616/202306161946.Kk7xeos8-lkp@intel.com/reproduce)

If you fix the issue in a separate patch/commit (i.e. not just a new version of
the same patch/commit), kindly add following tags
| Reported-by: kernel test robot <lkp at intel.com>
| Closes: https://lore.kernel.org/oe-kbuild-all/202306161946.Kk7xeos8-lkp@intel.com/

All warnings (new ones prefixed by >>):

   drivers/clk/meson/t7.c:7084:51: warning: initialized field overwritten [-Woverride-init]
    7084 |                 [CLKID_VID_PLL]                 = &t7_vid_pll.hw,
         |                                                   ^
   drivers/clk/meson/t7.c:7084:51: note: (near initialization for 't7_hw_onecell_data.hws[93]')
   drivers/clk/meson/t7.c: In function 'meson_t7_probe':
>> drivers/clk/meson/t7.c:7946:36: warning: variable 'mclk_data' set but not used [-Wunused-but-set-variable]
    7946 |         struct meson_clk_pll_data *mclk_data;
         |                                    ^~~~~~~~~
   drivers/clk/meson/t7.c: At top level:
   drivers/clk/meson/t7.c:689:37: warning: 't7_a73_dyn_clk_sel' defined but not used [-Wunused-const-variable=]
     689 | static const struct clk_parent_data t7_a73_dyn_clk_sel[] = {
         |                                     ^~~~~~~~~~~~~~~~~~
   drivers/clk/meson/t7.c:93:29: warning: 'meson_pll_clk_no_ops' defined but not used [-Wunused-const-variable=]
      93 | static const struct clk_ops meson_pll_clk_no_ops = {};
         |                             ^~~~~~~~~~~~~~~~~~~~


vim +/mclk_data +7946 drivers/clk/meson/t7.c

  7939	
  7940	static int __ref meson_t7_probe(struct platform_device *pdev)
  7941	{
  7942		struct device *dev = &pdev->dev;
  7943		struct regmap *basic_map;
  7944		struct regmap *pll_map;
  7945		struct regmap *cpu_clk_map;
> 7946		struct meson_clk_pll_data *mclk_data;
  7947		int ret, i;
  7948	
  7949		/* Get regmap for different clock area */
  7950		basic_map = t7_regmap_resource(dev, "basic");
  7951		if (IS_ERR(basic_map)) {
  7952			dev_err(dev, "basic clk registers not found\n");
  7953			return PTR_ERR(basic_map);
  7954		}
  7955	
  7956		pll_map = t7_regmap_resource(dev, "pll");
  7957		if (IS_ERR(pll_map)) {
  7958			dev_err(dev, "pll clk registers not found\n");
  7959			return PTR_ERR(pll_map);
  7960		}
  7961	
  7962		cpu_clk_map = t7_regmap_resource(dev, "cpu_clk");
  7963		if (IS_ERR(cpu_clk_map)) {
  7964			dev_err(dev, "cpu clk registers not found\n");
  7965			return PTR_ERR(cpu_clk_map);
  7966		}
  7967	
  7968		/* Populate regmap for the regmap backed clocks */
  7969		for (i = 0; i < ARRAY_SIZE(t7_clk_regmaps); i++)
  7970			t7_clk_regmaps[i]->map = basic_map;
  7971	
  7972		for (i = 0; i < ARRAY_SIZE(t7_cpu_clk_regmaps); i++)
  7973			t7_cpu_clk_regmaps[i]->map = cpu_clk_map;
  7974	
  7975		for (i = 0; i < ARRAY_SIZE(t7_pll_clk_regmaps); i++)
  7976			t7_pll_clk_regmaps[i]->map = pll_map;
  7977		regmap_write(pll_map, ANACTRL_MPLL_CTRL0, 0x00000543);
  7978	
  7979		mclk_data = t7_mclk_pll_dco.data;
  7980	
  7981		for (i = 0; i < t7_hw_onecell_data.num; i++) {
  7982			/* array might be sparse */
  7983			if (!t7_hw_onecell_data.hws[i])
  7984				continue;
  7985	
  7986			ret = devm_clk_hw_register(dev, t7_hw_onecell_data.hws[i]);
  7987			if (ret) {
  7988				dev_err(dev, "Clock registration failed\n");
  7989				return ret;
  7990			}
  7991		}
  7992		meson_t7_dvfs_setup(pdev);
  7993	
  7994	
  7995		return devm_of_clk_add_hw_provider(dev, of_clk_hw_onecell_get, &t7_hw_onecell_data);
  7996	}
  7997	

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