[PATCH v2 1/3] iommu: rockchip: Fix discovery table address encoding

[Jonas Karlman]

On 2023-06-15 23:24, Robin Murphy wrote:
> On 2023-06-15 21:10, Jonas Karlman wrote:
>> The address to the discovery table is currently encoded using the
>> following bit layout.
>>
>>   31:12 - Address bit 31:0
>>   11: 4 - Address bit 39:32
>>
>> This is also the bit layout used by the vendor kernel.
>>
>> However, testing has shown that addresses to the discovery/page tables
>> and memory pages are all encoded using the same bit layout.
>>
>> IOMMU v1:
>>   31:12 - Address bit 31:0
>>
>> IOMMU v2:
>>   31:12 - Address bit 31:0
>>   11: 8 - Address bit 35:32
>>    7: 4 - Address bit 39:36
>>
>> Change to use the mk_dtentries ops to encode the discovery table address
> 
> Nit: s/discovery/directory/g

Oops, will fix in entire series in a v3 :-)

> 
>> correctly. Also update the bit layout comment for the page address.
>>
>> These changes render the dte_addr_phys and dma_addr_dte ops unused
>> and will be removed in a following patch.
> 
> TBH I'd just squash that into this patch - we don't gain anything from 
> leaving dead code in stable kernels, and at worst it just stands to make 
> future fixes harder to backport.

Make sense, will squash them in v3.

> 
>> Fixes: 227014b33f62 ("iommu: rockchip: Add internal ops to handle variants")
>> Signed-off-by: Jonas Karlman <jonas at kwiboo.se>
>> ---
>> v2:
>> - replace currently with correctly in commit message
>>
>>   drivers/iommu/rockchip-iommu.c | 8 ++++----
>>   1 file changed, 4 insertions(+), 4 deletions(-)
>>
>> diff --git a/drivers/iommu/rockchip-iommu.c b/drivers/iommu/rockchip-iommu.c
>> index 4054030c3237..d46319f77e5c 100644
>> --- a/drivers/iommu/rockchip-iommu.c
>> +++ b/drivers/iommu/rockchip-iommu.c
>> @@ -278,8 +278,8 @@ static u32 rk_mk_pte(phys_addr_t page, int prot)
>>   /*
>>    * In v2:
>>    * 31:12 - Page address bit 31:0
>> - *  11:9 - Page address bit 34:32
>> - *   8:4 - Page address bit 39:35
>> + * 11: 8 - Page address bit 35:32
>> + *  7: 4 - Page address bit 39:36
>>    *     3 - Security
>>    *     2 - Writable
>>    *     1 - Readable
>> @@ -577,7 +577,7 @@ static void log_iova(struct rk_iommu *iommu, int index, dma_addr_t iova)
>>   	page_offset = rk_iova_page_offset(iova);
>>   
>>   	mmu_dte_addr = rk_iommu_read(base, RK_MMU_DTE_ADDR);
>> -	mmu_dte_addr_phys = rk_ops->dte_addr_phys(mmu_dte_addr);
>> +	mmu_dte_addr_phys = rk_ops->pt_address(mmu_dte_addr);
>>   
>>   	dte_addr_phys = mmu_dte_addr_phys + (4 * dte_index);
>>   	dte_addr = phys_to_virt(dte_addr_phys);
>> @@ -967,7 +967,7 @@ static int rk_iommu_enable(struct rk_iommu *iommu)
>>   
>>   	for (i = 0; i < iommu->num_mmu; i++) {
>>   		rk_iommu_write(iommu->bases[i], RK_MMU_DTE_ADDR,
>> -			       rk_ops->dma_addr_dte(rk_domain->dt_dma));
>> +			       rk_ops->mk_dtentries(rk_domain->dt_dma));
> 
> Hmm, this writes the RK_DTE_PT_VALID bit into the register as well - 
> does that really make sense?

On v1 bit 11:0 behave as read-only and on v2 bit 3:0 behave read-only.
Writing anything to those bits read back as 0, so was safe to write
RK_DTE_PT_VALID. Should probably mention this in a comment in v3.

Regards,
Jonas

> 
> Thanks,
> Robin.
> 
>>   		rk_iommu_base_command(iommu->bases[i], RK_MMU_CMD_ZAP_CACHE);
>>   		rk_iommu_write(iommu->bases[i], RK_MMU_INT_MASK, RK_MMU_IRQ_MASK);
>>   	}