[PATCH] arm64/mm: remove now-superfluous ISBs from TTBR writes

[Catalin Marinas]

On Tue, 13 Jun 2023 15:19:59 +0100, Jamie Iles wrote:
> At the time of authoring 7655abb95386 ("arm64: mm: Move ASID from TTBR0
> to TTBR1"), the Arm ARM did not specify any ordering guarantees for
> direct writes to TTBR0_ELx and TTBR1_ELx and so an ISB was required
> after each write to ensure TLBs would only be populated from the
> expected (or reserved tables).
> 
> In a recent update to the Arm ARM, the requirements have been relaxed to
> reflect the implementation of current CPUs and required implementation
> of future CPUs to read (RDYDPX in D8.2.3 Translation table base address
> register):
> 
> [...]

Applied to arm64 (for-next/misc), thanks!

[1/1] arm64/mm: remove now-superfluous ISBs from TTBR writes
      https://git.kernel.org/arm64/c/b9293d457ff3

-- 
Catalin