[PATCH] arm64/mm: remove now-superfluous ISBs from TTBR writes

[Jamie Iles]

Hi Anshuman,

On Wed, Jun 14, 2023 at 03:35:03PM +0530, Anshuman Khandual wrote:
> 
> 
> On 6/13/23 19:49, Jamie Iles wrote:
> > At the time of authoring 7655abb95386 ("arm64: mm: Move ASID from TTBR0
> > to TTBR1"), the Arm ARM did not specify any ordering guarantees for
> > direct writes to TTBR0_ELx and TTBR1_ELx and so an ISB was required
> > after each write to ensure TLBs would only be populated from the
> > expected (or reserved tables).
> > 
> > In a recent update to the Arm ARM, the requirements have been relaxed to
> > reflect the implementation of current CPUs and required implementation
> > of future CPUs to read (RDYDPX in D8.2.3 Translation table base address
> > register):
> 
> But what about the existing CPUs that might still require an ISB after
> each individual write into TTBR0/1_EL1 ? Would they be impacted if the
> ISB get dropped ?

For this retrospective change Arm verify that this is the current 
behaviour of existing CPUs both by Arm Ltd and licensees.  There should 
be no current CPUs that require these ISBs.

Thanks,

Jamie