[PATCH v2 1/1] arm64: dts: imx8mp: Add coresight trace components

[Rob Herring]

On Mon, May 15, 2023 at 9:02 AM Frank Li <Frank.Li at nxp.com> wrote:
>
> Add coresight trace components (ETM, ETF, ETB and Funnel).
>
> ┌───────┐  ┌───────┐  ┌───────┐
> │ CPU0  ├─►│ ETM0  ├─►│       │
> └───────┘  └───────┘  │       │
>                       │       │
> ┌───────┐  ┌───────┐  │  ATP  │
> │ CPU1  ├─►│ ETM1  ├─►│       │
> └───────┘  └───────┘  │       │
>                       │ FUNNEL│
> ┌───────┐  ┌───────┐  │       │
> │ CPU2  ├─►│ ETM2  ├─►│       │
> └───────┘  └───────┘  │       │   ┌─────┐  ┌─────┐
>                       │       │   │     │  │     │
> ┌───────┐  ┌───────┐  │       │   │ M7  │  │ DSP │
> │ CPU3  ├─►│ ETM3  ├─►│       │   │     │  │     │
> └───────┘  └───────┘  └───┬───┘   └──┬──┘  └──┬──┘               AXI
>                           │          │        │                   ▲
>                           ▼          ▼        ▼                   │
>                       ┌───────────────────────────┐   ┌─────┐   ┌─┴──┐
>                       │          ATP FUNNEL       ├──►│ETF  ├─► │ETR │
>                       └───────────────────────────┘   └─────┘   └────┘
>
> Signed-off-by: Frank Li <Frank.Li at nxp.com>
> ---
> Change from v1 to v2
> - add new line between nodes
> - add new line between properties and child node
>
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 204 ++++++++++++++++++++++
>  1 file changed, 204 insertions(+)
>
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> index a19224fe1a6a..1a25710c3a90 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -304,6 +304,210 @@ soc: soc at 0 {
>                 nvmem-cells = <&imx8mp_uid>;
>                 nvmem-cell-names = "soc_unique_id";
>
> +               etm0: etm at 28440000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0x28440000 0x10000>;
> +                       arm,primecell-periphid = <0xbb95d>;
> +                       cpu = <&A53_0>;
> +                       clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
> +                       clock-names = "apb_pclk";
> +
> +                       out-ports {
> +                               port {
> +                                       etm0_out_port: endpoint {
> +                                               remote-endpoint = <&ca_funnel_in_port0>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etm1: etm at 28540000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0x28540000 0x10000>;
> +                       arm,primecell-periphid = <0xbb95d>;
> +                       cpu = <&A53_1>;
> +                       clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
> +                       clock-names = "apb_pclk";
> +
> +                       out-ports {
> +                               port {
> +                                       etm1_out_port: endpoint {
> +                                               remote-endpoint = <&ca_funnel_in_port1>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etm2: etm at 28640000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0x28640000 0x10000>;
> +                       arm,primecell-periphid = <0xbb95d>;
> +                       cpu = <&A53_2>;
> +                       clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
> +                       clock-names = "apb_pclk";
> +
> +                       out-ports {
> +                               port {
> +                                       etm2_out_port: endpoint {
> +                                               remote-endpoint = <&ca_funnel_in_port2>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               etm3: etm at 28740000 {
> +                       compatible = "arm,coresight-etm4x", "arm,primecell";
> +                       reg = <0x28740000 0x10000>;
> +                       arm,primecell-periphid = <0xbb95d>;
> +                       cpu = <&A53_3>;
> +                       clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
> +                       clock-names = "apb_pclk";
> +
> +                       out-ports {
> +                               port {
> +                                       etm3_out_port: endpoint {
> +                                               remote-endpoint = <&ca_funnel_in_port3>;
> +                                       };
> +                               };
> +                       };
> +               };
> +
> +               funnel {
> +                       /*
> +                        * non-configurable funnel don't show up on the AMBA
> +                        * bus.  As such no need to add "arm,primecell".
> +                        */
> +                       compatible = "arm,coresight-static-funnel";

This device has no registers so it should not be under the bus node.

This is pointed out by the dtschema checks. Please don't add new ones.

Rob