[PATCH 1/1] arm64: dts: imx8mp: Add coresight trace components

[Alexander Stein]

Hi,

Am Freitag, 5. Mai 2023, 21:51:51 CEST schrieb Frank Li:
> Add coresight trace components (ETM, ETF, ETB and Funnel).
> 
> ┌───────┐  ┌───────┐  ┌───────┐
> │ CPU0  ├─►│ ETM0  ├─►│       │
> └───────┘  └───────┘  │       │
>                       │       │
> ┌───────┐  ┌───────┐  │  ATP  │
> │ CPU1  ├─►│ ETM1  ├─►│       │
> └───────┘  └───────┘  │       │
>                       │ FUNNEL│
> ┌───────┐  ┌───────┐  │       │
> │ CPU2  ├─►│ ETM2  ├─►│       │
> └───────┘  └───────┘  │       │   ┌─────┐  ┌─────┐
>                       │       │   │     │  │     │
> ┌───────┐  ┌───────┐  │       │   │ M7  │  │ DSP │
> │ CPU3  ├─►│ ETM3  ├─►│       │   │     │  │     │
> └───────┘  └───────┘  └───┬───┘   └──┬──┘  └──┬──┘               AXI
>                           │          │        │                   ▲
>                           ▼          ▼        ▼                   │
>                       ┌───────────────────────────┐   ┌─────┐   ┌─┴──┐
>                       │          ATP FUNNEL       ├──►│ETF  ├─► │ETR │
>                       └───────────────────────────┘   └─────┘   └────┘
> 
> Signed-off-by: Frank Li <Frank.Li at nxp.com>
> ---
>  arch/arm64/boot/dts/freescale/imx8mp.dtsi | 179 ++++++++++++++++++++++
>  1 file changed, 179 insertions(+)
> 
> diff --git a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> b/arch/arm64/boot/dts/freescale/imx8mp.dtsi index
> a19224fe1a6a..0fa74477b9e1 100644
> --- a/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> +++ b/arch/arm64/boot/dts/freescale/imx8mp.dtsi
> @@ -304,6 +304,185 @@ soc: soc at 0 {
>  		nvmem-cells = <&imx8mp_uid>;
>  		nvmem-cell-names = "soc_unique_id";
> 
> +		etm0: etm at 28440000 {
> +			compatible = "arm,coresight-etm4x", 
"arm,primecell";
> +			reg = <0x28440000 0x10000>;
> +			arm,primecell-periphid = <0xbb95d>;
> +			cpu = <&A53_0>;
> +			clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
> +			clock-names = "apb_pclk";
> +			out-ports {
> +				port {
> +					etm0_out_port: endpoint {
> +						remote-endpoint = 
<&ca_funnel_in_port0>;
> +					};
> +				};
> +			};
> +		};
> +
> +		etm1: etm at 28540000 {
> +			compatible = "arm,coresight-etm4x", 
"arm,primecell";
> +			reg = <0x28540000 0x10000>;
> +			arm,primecell-periphid = <0xbb95d>;
> +			cpu = <&A53_1>;
> +			clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
> +			clock-names = "apb_pclk";
> +			out-ports {
> +				port {
> +					etm1_out_port: endpoint {
> +						remote-endpoint = 
<&ca_funnel_in_port1>;
> +					};
> +				};
> +			};
> +		};
> +
> +		etm2: etm at 28640000 {
> +			compatible = "arm,coresight-etm4x", 
"arm,primecell";
> +			reg = <0x28640000 0x10000>;
> +			arm,primecell-periphid = <0xbb95d>;
> +			cpu = <&A53_2>;
> +			clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
> +			clock-names = "apb_pclk";
> +			out-ports {
> +				port {
> +					etm2_out_port: endpoint {
> +						remote-endpoint = 
<&ca_funnel_in_port2>;
> +					};
> +				};
> +			};
> +		};
> +
> +		etm3: etm at 28740000 {
> +			compatible = "arm,coresight-etm4x", 
"arm,primecell";
> +			reg = <0x28740000 0x10000>;
> +			arm,primecell-periphid = <0xbb95d>;
> +			cpu = <&A53_3>;
> +			clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
> +			clock-names = "apb_pclk";
> +			out-ports {
> +				port {
> +					etm3_out_port: endpoint {
> +						remote-endpoint = 
<&ca_funnel_in_port3>;
> +					};
> +				};
> +			};
> +		};
> +
> +		funnel {
> +			/*
> +			 * non-configurable funnel don't show up on the 
AMBA
> +			 * bus.  As such no need to add "arm,primecell".
> +			 */
> +			compatible = "arm,coresight-static-funnel";
> +			in-ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				port at 0 {
> +					reg = <0>;
> +					ca_funnel_in_port0: endpoint 
{
> +						remote-endpoint = 
<&etm0_out_port>;
> +					};
> +				};
> +				port at 1 {
> +					reg = <1>;
> +					ca_funnel_in_port1: endpoint 
{
> +						remote-endpoint = 
<&etm1_out_port>;
> +					};
> +				};
> +				port at 2 {
> +					reg = <2>;
> +					ca_funnel_in_port2: endpoint 
{
> +						remote-endpoint = 
<&etm2_out_port>;
> +					};
> +				};
> +				port at 3 {
> +					reg = <3>;
> +					ca_funnel_in_port3: endpoint 
{
> +						remote-endpoint = 
<&etm3_out_port>;
> +					};
> +				};
> +			};
> +			out-ports {
> +				port {
> +					ca_funnel_out_port0: 
endpoint {
> +						remote-endpoint = 
<&hugo_funnel_in_port0>;
> +					};
> +				};
> +			};
> +		};
> +
> +		funnel at 28c03000 {
> +			compatible = "arm,coresight-dynamic-funnel", 
"arm,primecell";
> +			reg = <0x28c03000 0x1000>;
> +			clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
> +			clock-names = "apb_pclk";
> +			in-ports {
> +				#address-cells = <1>;
> +				#size-cells = <0>;
> +				port at 0 {
> +					reg = <0>;
> +					hugo_funnel_in_port0: 
endpoint {
> +						remote-endpoint = 
<&ca_funnel_out_port0>;
> +					};
> +				};
> +				port at 1 {
> +					reg = <1>;
> +					hugo_funnel_in_port1: 
endpoint {
> +					/* M7 input */
> +					};
> +				};
> +				port at 2 {
> +					reg = <2>;
> +					hugo_funnel_in_port2: 
endpoint {
> +					/* DSP input */
> +					};
> +				};
> +				/* the other input ports are not 
connect to anything */
> +			};
> +			out-ports {
> +				port {
> +					hugo_funnel_out_port0: 
endpoint {
> +						remote-endpoint = 
<&etf_in_port>;
> +					};
> +				};
> +			};
> +		};
> +
> +		etf at 28c04000 {

The reference manual states "CXTMC_ETB" for this address. I don't have much 
knowledge about coresight, but ETB is not the same as ETF, right? Which one is 
correct?

Best regards,
Alexander

> +			compatible = "arm,coresight-tmc", 
"arm,primecell";
> +			reg = <0x28c04000 0x1000>;
> +			clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
> +			clock-names = "apb_pclk";
> +			in-ports {
> +				port {
> +					etf_in_port: endpoint {
> +						remote-endpoint = 
<&hugo_funnel_out_port0>;
> +					};
> +				};
> +			};
> +			out-ports {
> +				port {
> +					etf_out_port: endpoint {
> +						remote-endpoint = 
<&etr_in_port>;
> +					};
> +				};
> +			};
> +		};
> +
> +		etr at 28c06000 {
> +			compatible = "arm,coresight-tmc", 
"arm,primecell";
> +			reg = <0x28c06000 0x1000>;
> +			clocks = <&clk IMX8MP_CLK_MAIN_AXI>;
> +			clock-names = "apb_pclk";
> +			in-ports {
> +				port {
> +					etr_in_port: endpoint {
> +						remote-endpoint = 
<&etf_out_port>;
> +					};
> +				};
> +			};
> +		};
> +
>  		aips1: bus at 30000000 {
>  			compatible = "fsl,aips-bus", "simple-bus";
>  			reg = <0x30000000 0x400000>;


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