[PATCH] coresight: etm4x: Match all ETM4 instances based on DEVARCH and DEVTYPE

[Suzuki K Poulose]

On 07/06/2023 11:43, Mike Leach wrote:
> On Mon, 5 Jun 2023 at 14:30, Suzuki K Poulose <suzuki.poulose at arm.com> wrote:
>>
>> Instead of adding the PIDs forever to the list for the new CPUs, let us detect
>> a component to be ETMv4 based on the CoreSight CID, DEVTYPE=PE_TRACE and
>> DEVARCH=ETMv4. This is already done for some of the ETMs. We can extend the PID
>> matching to match the PIDR2:JEDEC, BIT[3], which must be 1 (RA0) always.

Fix RA0 => RAO

>>
>> Link: https://lkml.kernel.org/r/20230317030501.1811905-1-anshuman.khandual@arm.com
>> Cc: Anshuman Khandual <anshuman.khandual at arm.com>
>> Cc: Rob Herring <robh+dt at kernel.org>
>> Cc: frowand.list at gmail.com
>> Cc: linux at armlinux.org.uk
>> Cc: Mike Leach <mike.leach at linaro.org>
>> Signed-off-by: Suzuki K Poulose <suzuki.poulose at arm.com>

>> +#define PIDR2_JEDEC                    BIT(3)
>> +#define PID_PIDR2_JEDEC                        (PIDR2_JEDEC << 16)
>> +/*
>> + * Match all PIDs in a given CoreSight device type and architecture, defined
>> + * by the uci.
>> + */
>> +#define CS_AMBA_MATCH_ALL_UCI(uci)                                     \
>> +       __CS_AMBA_UCI_ID(PID_PIDR2_JEDEC, PID_PIDR2_JEDEC, uci)
>>
>>   /* extract the data value from a UCI structure given amba_id pointer. */
>>   static inline void *coresight_get_uci_data(const struct amba_id *id)
>> --
>> 2.34.1
>>
> Reviewed by:- Mike Leach <mike.leach at linaro.org>
> 

Thanks Mike, I have queued this, with the above fix:

[01] https://git.kernel.org/coresight/c/ab5ca6268afc