[PATCH 2/4] arm64: dts: mediatek: mt8186: Wire up CPU frequency/voltage scaling
Chen-Yu Tsai
wenst at chromium.org
Wed Jun 7 02:06:50 PDT 2023
This adds clocks, dynamic power coefficients, and OPP tables for the CPU
cores, so that everything required at the SoC level for CPU freqency and
voltage scaling is available.
Signed-off-by: Chen-Yu Tsai <wenst at chromium.org>
---
arch/arm64/boot/dts/mediatek/mt8186.dtsi | 274 +++++++++++++++++++++++
1 file changed, 274 insertions(+)
diff --git a/arch/arm64/boot/dts/mediatek/mt8186.dtsi b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
index 1b754f7a0725..6735c1feb26d 100644
--- a/arch/arm64/boot/dts/mediatek/mt8186.dtsi
+++ b/arch/arm64/boot/dts/mediatek/mt8186.dtsi
@@ -136,6 +136,240 @@ cci_opp_15: opp-1400000000 {
};
};
+ cluster0_opp: opp-table-cluster0 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-500000000 {
+ opp-hz = /bits/ 64 <500000000>;
+ opp-microvolt = <600000>;
+ opp-level = <15>;
+ required-opps = <&cci_opp_0>;
+ };
+
+ opp-774000000 {
+ opp-hz = /bits/ 64 <774000000>;
+ opp-microvolt = <675000>;
+ opp-level = <14>;
+ required-opps = <&cci_opp_1>;
+ };
+
+ opp-875000000 {
+ opp-hz = /bits/ 64 <875000000>;
+ opp-microvolt = <700000>;
+ opp-level = <13>;
+ required-opps = <&cci_opp_2>;
+ };
+
+ opp-975000000 {
+ opp-hz = /bits/ 64 <975000000>;
+ opp-microvolt = <725000>;
+ opp-level = <12>;
+ required-opps = <&cci_opp_3>;
+ };
+
+ opp-1075000000 {
+ opp-hz = /bits/ 64 <1075000000>;
+ opp-microvolt = <750000>;
+ opp-level = <11>;
+ required-opps = <&cci_opp_4>;
+ };
+
+ opp-1175000000 {
+ opp-hz = /bits/ 64 <1175000000>;
+ opp-microvolt = <775000>;
+ opp-level = <10>;
+ required-opps = <&cci_opp_5>;
+ };
+
+ opp-1275000000 {
+ opp-hz = /bits/ 64 <1275000000>;
+ opp-microvolt = <800000>;
+ opp-level = <9>;
+ required-opps = <&cci_opp_6>;
+ };
+
+ opp-1375000000 {
+ opp-hz = /bits/ 64 <1375000000>;
+ opp-microvolt = <825000>;
+ opp-level = <8>;
+ required-opps = <&cci_opp_7>;
+ };
+
+ opp-1500000000 {
+ opp-hz = /bits/ 64 <1500000000>;
+ opp-microvolt = <856250>;
+ opp-level = <7>;
+ required-opps = <&cci_opp_8>;
+ };
+
+ opp-1618000000 {
+ opp-hz = /bits/ 64 <1618000000>;
+ opp-microvolt = <875000>;
+ opp-level = <6>;
+ required-opps = <&cci_opp_9>;
+ };
+
+ opp-1666000000 {
+ opp-hz = /bits/ 64 <1666000000>;
+ opp-microvolt = <900000>;
+ opp-level = <5>;
+ required-opps = <&cci_opp_10>;
+ };
+
+ opp-1733000000 {
+ opp-hz = /bits/ 64 <1733000000>;
+ opp-microvolt = <925000>;
+ opp-level = <4>;
+ required-opps = <&cci_opp_11>;
+ };
+
+ opp-1800000000 {
+ opp-hz = /bits/ 64 <1800000000>;
+ opp-microvolt = <950000>;
+ opp-level = <3>;
+ required-opps = <&cci_opp_12>;
+ };
+
+ opp-1866000000 {
+ opp-hz = /bits/ 64 <1866000000>;
+ opp-microvolt = <981250>;
+ opp-level = <2>;
+ required-opps = <&cci_opp_13>;
+ };
+
+ opp-1933000000 {
+ opp-hz = /bits/ 64 <1933000000>;
+ opp-microvolt = <1006250>;
+ opp-level = <1>;
+ required-opps = <&cci_opp_14>;
+ };
+
+ opp-2000000000 {
+ opp-hz = /bits/ 64 <2000000000>;
+ opp-microvolt = <1031250>;
+ opp-level = <0>;
+ required-opps = <&cci_opp_15>;
+ };
+ };
+
+ cluster1_opp: opp-table-cluster1 {
+ compatible = "operating-points-v2";
+ opp-shared;
+
+ opp-774000000 {
+ opp-hz = /bits/ 64 <774000000>;
+ opp-microvolt = <675000>;
+ opp-level = <15>;
+ required-opps = <&cci_opp_0>;
+ };
+
+ opp-835000000 {
+ opp-hz = /bits/ 64 <835000000>;
+ opp-microvolt = <693750>;
+ opp-level = <14>;
+ required-opps = <&cci_opp_1>;
+ };
+
+ opp-919000000 {
+ opp-hz = /bits/ 64 <919000000>;
+ opp-microvolt = <718750>;
+ opp-level = <13>;
+ required-opps = <&cci_opp_2>;
+ };
+
+ opp-1002000000 {
+ opp-hz = /bits/ 64 <1002000000>;
+ opp-microvolt = <743750>;
+ opp-level = <12>;
+ required-opps = <&cci_opp_3>;
+ };
+
+ opp-1085000000 {
+ opp-hz = /bits/ 64 <1085000000>;
+ opp-microvolt = <775000>;
+ opp-level = <11>;
+ required-opps = <&cci_opp_4>;
+ };
+
+ opp-1169000000 {
+ opp-hz = /bits/ 64 <1169000000>;
+ opp-microvolt = <800000>;
+ opp-level = <10>;
+ required-opps = <&cci_opp_5>;
+ };
+
+ opp-1308000000 {
+ opp-hz = /bits/ 64 <1308000000>;
+ opp-microvolt = <843750>;
+ opp-level = <9>;
+ required-opps = <&cci_opp_6>;
+ };
+
+ opp-1419000000 {
+ opp-hz = /bits/ 64 <1419000000>;
+ opp-microvolt = <875000>;
+ opp-level = <8>;
+ required-opps = <&cci_opp_7>;
+ };
+
+ opp-1530000000 {
+ opp-hz = /bits/ 64 <1530000000>;
+ opp-microvolt = <912500>;
+ opp-level = <7>;
+ required-opps = <&cci_opp_8>;
+ };
+
+ opp-1670000000 {
+ opp-hz = /bits/ 64 <1670000000>;
+ opp-microvolt = <956250>;
+ opp-level = <6>;
+ required-opps = <&cci_opp_9>;
+ };
+
+ opp-1733000000 {
+ opp-hz = /bits/ 64 <1733000000>;
+ opp-microvolt = <981250>;
+ opp-level = <5>;
+ required-opps = <&cci_opp_10>;
+ };
+
+ opp-1796000000 {
+ opp-hz = /bits/ 64 <1796000000>;
+ opp-microvolt = <1012500>;
+ opp-level = <4>;
+ required-opps = <&cci_opp_11>;
+ };
+
+ opp-1860000000 {
+ opp-hz = /bits/ 64 <1860000000>;
+ opp-microvolt = <1037500>;
+ opp-level = <3>;
+ required-opps = <&cci_opp_12>;
+ };
+
+ opp-1923000000 {
+ opp-hz = /bits/ 64 <1923000000>;
+ opp-microvolt = <1062500>;
+ opp-level = <2>;
+ required-opps = <&cci_opp_13>;
+ };
+
+ cluster1_opp_14: opp-1986000000 {
+ opp-hz = /bits/ 64 <1986000000>;
+ opp-microvolt = <1093750>;
+ opp-level = <1>;
+ required-opps = <&cci_opp_14>;
+ };
+
+ cluster1_opp_15: opp-2050000000 {
+ opp-hz = /bits/ 64 <2050000000>;
+ opp-microvolt = <1118750>;
+ opp-level = <0>;
+ required-opps = <&cci_opp_15>;
+ };
+ };
+
cpus {
#address-cells = <1>;
#size-cells = <0>;
@@ -182,6 +416,11 @@ cpu0: cpu at 0 {
reg = <0x000>;
enable-method = "psci";
clock-frequency = <2000000000>;
+ clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
+ dynamic-power-coefficient = <84>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
i-cache-size = <32768>;
@@ -201,6 +440,11 @@ cpu1: cpu at 100 {
reg = <0x100>;
enable-method = "psci";
clock-frequency = <2000000000>;
+ clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
+ dynamic-power-coefficient = <84>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
i-cache-size = <32768>;
@@ -220,6 +464,11 @@ cpu2: cpu at 200 {
reg = <0x200>;
enable-method = "psci";
clock-frequency = <2000000000>;
+ clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
+ dynamic-power-coefficient = <84>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
i-cache-size = <32768>;
@@ -239,6 +488,11 @@ cpu3: cpu at 300 {
reg = <0x300>;
enable-method = "psci";
clock-frequency = <2000000000>;
+ clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
+ dynamic-power-coefficient = <84>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
i-cache-size = <32768>;
@@ -258,6 +512,11 @@ cpu4: cpu at 400 {
reg = <0x400>;
enable-method = "psci";
clock-frequency = <2000000000>;
+ clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
+ dynamic-power-coefficient = <84>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
i-cache-size = <32768>;
@@ -277,6 +536,11 @@ cpu5: cpu at 500 {
reg = <0x500>;
enable-method = "psci";
clock-frequency = <2000000000>;
+ clocks = <&mcusys CLK_MCU_ARMPLL_LL_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster0_opp>;
+ dynamic-power-coefficient = <84>;
capacity-dmips-mhz = <382>;
cpu-idle-states = <&cpu_ret_l &cpu_off_l>;
i-cache-size = <32768>;
@@ -296,6 +560,11 @@ cpu6: cpu at 600 {
reg = <0x600>;
enable-method = "psci";
clock-frequency = <2050000000>;
+ clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
+ dynamic-power-coefficient = <335>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
i-cache-size = <65536>;
@@ -315,6 +584,11 @@ cpu7: cpu at 700 {
reg = <0x700>;
enable-method = "psci";
clock-frequency = <2050000000>;
+ clocks = <&mcusys CLK_MCU_ARMPLL_BL_SEL>,
+ <&apmixedsys CLK_APMIXED_MAINPLL>;
+ clock-names = "cpu", "intermediate";
+ operating-points-v2 = <&cluster1_opp>;
+ dynamic-power-coefficient = <335>;
capacity-dmips-mhz = <1024>;
cpu-idle-states = <&cpu_ret_b &cpu_off_b>;
i-cache-size = <65536>;
--
2.41.0.rc0.172.g3f132b7071-goog
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