[PATCH v2] meson saradc: fix clock divider mask length

[Andy Shevchenko]

On Tue, Jun 06, 2023 at 04:50:17PM +0300, George Stark wrote:
> According to datasheets of supported meson SOCs
> length of ADC_CLK_DIV field is 6 bits long.
> Although all supported SOCs have the register with the
> field ADC_CLK_DIV documented later SOCs use external clock
> rather than ADC internal clock so
> this patch affects only meson8 family (S8* SOCs)

The longest line above has 60 characters, isn't it too wasteful?
Can you make it ~72?

Code wise looks good to me.

-- 
With Best Regards,
Andy Shevchenko