[RFC] arm-mpam: how to define mpam cache reference

[James Morse]

Hi Wang ShaoBo,

(CC: +linux-arm-kernel at lists.infradead.org ... linux-arm at vger.kernel.org isn't a thing)

On 05/06/2023 11:23, Wangshaobo (bobo) wrote:
> I checked the protocol specification of MPAM ACPI V2 from https://developer.arm.com
> /documentation/den0065/latest锟斤拷
> The explanation for the cache locator part is as following:
> 
> ```
> The cache locator is described in terms of the cache锟斤拷s topological position within
> the processor hierarchy.
> 
> The position is derived from the ACPI PPTT table [2] , and is expressed as a reference to
> the cache (Type 1) structure within the PPTT table that describes the cache...
> 
> ...
> Cache reference : This field must match the Identifier field of the
> PPTT Type 1 structure that describes this cache.
> 
> ```
> 
> And your code branch (https://git.kernel.org/pub/scm/linux/kernel/git/morse/linux.git)
> directly uses the cache id to index the location of the cache node, and also requires PPTT
> revision >=3:

[...]

> So if my PPTT revision < 3, could we traverse all cache nodes in PPTT by giving an offset?

Absolutely not. Having a byte offset between tables is an nightmare to work with. Your
UEFI firmware may generate or modify the tables at boot. Having byte-offsets between them
means you end up with a tangled web of tables that have to be re-generated. The OS then
has to parse the full table every time to check the byte-offset lands on a sensible boundary.

Please update your PPTT to support identifying the caches. MPAM depends on this to which
cache is which.


> and to get the cache level and finally link all cache nodes with the same PPTT_ref to same
> mpam component,this is your earlier code:

Yup, I wrote this while arguing with the spec folk that we shouldn't do this. It never
made it into a published version of the ACPI spec.



Thanks,

James