[PATCH v2 04/26] arm64: Add TLBI operation encodings

Fri Jul 28 08:49:50 PDT 2023

Hi Marc,

> On 28 Jul 2023, at 08:29, Marc Zyngier <maz at kernel.org> wrote:
> 
> Add all the TLBI encodings that are usable from Non-Secure.
> 
> Reviewed-by: Eric Auger <eric.auger at redhat.com>
> Signed-off-by: Marc Zyngier <maz at kernel.org>
> ---
> arch/arm64/include/asm/sysreg.h | 128 ++++++++++++++++++++++++++++++++
> 1 file changed, 128 insertions(+)
> 
> diff --git a/arch/arm64/include/asm/sysreg.h b/arch/arm64/include/asm/sysreg.h
> index 5084add86897..72e18480ce62 100644
> --- a/arch/arm64/include/asm/sysreg.h
> +++ b/arch/arm64/include/asm/sysreg.h
> @@ -514,6 +514,134 @@
> 
> #define SYS_SP_EL2 sys_reg(3, 6,  4, 1, 0)
> 
> +/* TLBI instructions */
> +#define OP_TLBI_VMALLE1OS sys_insn(1, 0, 8, 1, 0)
> +#define OP_TLBI_VAE1OS sys_insn(1, 0, 8, 1, 1)
> +#define OP_TLBI_ASIDE1OS sys_insn(1, 0, 8, 1, 2)
> +#define OP_TLBI_VAAE1OS sys_insn(1, 0, 8, 1, 3)
> +#define OP_TLBI_VALE1OS sys_insn(1, 0, 8, 1, 5)
> +#define OP_TLBI_VAALE1OS sys_insn(1, 0, 8, 1, 7)
> +#define OP_TLBI_RVAE1IS sys_insn(1, 0, 8, 2, 1)
> +#define OP_TLBI_RVAAE1IS sys_insn(1, 0, 8, 2, 3)
> +#define OP_TLBI_RVALE1IS sys_insn(1, 0, 8, 2, 5)
> +#define OP_TLBI_RVAALE1IS sys_insn(1, 0, 8, 2, 7)
> +#define OP_TLBI_VMALLE1IS sys_insn(1, 0, 8, 3, 0)
> +#define OP_TLBI_VAE1IS sys_insn(1, 0, 8, 3, 1)
> +#define OP_TLBI_ASIDE1IS sys_insn(1, 0, 8, 3, 2)
> +#define OP_TLBI_VAAE1IS sys_insn(1, 0, 8, 3, 3)
> +#define OP_TLBI_VALE1IS sys_insn(1, 0, 8, 3, 5)
> +#define OP_TLBI_VAALE1IS sys_insn(1, 0, 8, 3, 7)
> +#define OP_TLBI_RVAE1OS sys_insn(1, 0, 8, 5, 1)
> +#define OP_TLBI_RVAAE1OS sys_insn(1, 0, 8, 5, 3)
> +#define OP_TLBI_RVALE1OS sys_insn(1, 0, 8, 5, 5)
> +#define OP_TLBI_RVAALE1OS sys_insn(1, 0, 8, 5, 7)
> +#define OP_TLBI_RVAE1 sys_insn(1, 0, 8, 6, 1)
> +#define OP_TLBI_RVAAE1 sys_insn(1, 0, 8, 6, 3)
> +#define OP_TLBI_RVALE1 sys_insn(1, 0, 8, 6, 5)
> +#define OP_TLBI_RVAALE1 sys_insn(1, 0, 8, 6, 7)
> +#define OP_TLBI_VMALLE1 sys_insn(1, 0, 8, 7, 0)
> +#define OP_TLBI_VAE1 sys_insn(1, 0, 8, 7, 1)
> +#define OP_TLBI_ASIDE1 sys_insn(1, 0, 8, 7, 2)
> +#define OP_TLBI_VAAE1 sys_insn(1, 0, 8, 7, 3)
> +#define OP_TLBI_VALE1 sys_insn(1, 0, 8, 7, 5)
> +#define OP_TLBI_VAALE1 sys_insn(1, 0, 8, 7, 7)
> +#define OP_TLBI_VMALLE1OSNXS sys_insn(1, 0, 9, 1, 0)
> +#define OP_TLBI_VAE1OSNXS sys_insn(1, 0, 9, 1, 1)
> +#define OP_TLBI_ASIDE1OSNXS sys_insn(1, 0, 9, 1, 2)
> +#define OP_TLBI_VAAE1OSNXS sys_insn(1, 0, 9, 1, 3)
> +#define OP_TLBI_VALE1OSNXS sys_insn(1, 0, 9, 1, 5)
> +#define OP_TLBI_VAALE1OSNXS sys_insn(1, 0, 9, 1, 7)
> +#define OP_TLBI_RVAE1ISNXS sys_insn(1, 0, 9, 2, 1)
> +#define OP_TLBI_RVAAE1ISNXS sys_insn(1, 0, 9, 2, 3)
> +#define OP_TLBI_RVALE1ISNXS sys_insn(1, 0, 9, 2, 5)
> +#define OP_TLBI_RVAALE1ISNXS sys_insn(1, 0, 9, 2, 7)
> +#define OP_TLBI_VMALLE1ISNXS sys_insn(1, 0, 9, 3, 0)
> +#define OP_TLBI_VAE1ISNXS sys_insn(1, 0, 9, 3, 1)
> +#define OP_TLBI_ASIDE1ISNXS sys_insn(1, 0, 9, 3, 2)
> +#define OP_TLBI_VAAE1ISNXS sys_insn(1, 0, 9, 3, 3)
> +#define OP_TLBI_VALE1ISNXS sys_insn(1, 0, 9, 3, 5)
> +#define OP_TLBI_VAALE1ISNXS sys_insn(1, 0, 9, 3, 7)
> +#define OP_TLBI_RVAE1OSNXS sys_insn(1, 0, 9, 5, 1)
> +#define OP_TLBI_RVAAE1OSNXS sys_insn(1, 0, 9, 5, 3)
> +#define OP_TLBI_RVALE1OSNXS sys_insn(1, 0, 9, 5, 5)
> +#define OP_TLBI_RVAALE1OSNXS sys_insn(1, 0, 9, 5, 7)
> +#define OP_TLBI_RVAE1NXS sys_insn(1, 0, 9, 6, 1)
> +#define OP_TLBI_RVAAE1NXS sys_insn(1, 0, 9, 6, 3)
> +#define OP_TLBI_RVALE1NXS sys_insn(1, 0, 9, 6, 5)
> +#define OP_TLBI_RVAALE1NXS sys_insn(1, 0, 9, 6, 7)
> +#define OP_TLBI_VMALLE1NXS sys_insn(1, 0, 9, 7, 0)
> +#define OP_TLBI_VAE1NXS sys_insn(1, 0, 9, 7, 1)
> +#define OP_TLBI_ASIDE1NXS sys_insn(1, 0, 9, 7, 2)
> +#define OP_TLBI_VAAE1NXS sys_insn(1, 0, 9, 7, 3)
> +#define OP_TLBI_VALE1NXS sys_insn(1, 0, 9, 7, 5)
> +#define OP_TLBI_VAALE1NXS sys_insn(1, 0, 9, 7, 7)
> +#define OP_TLBI_IPAS2E1IS sys_insn(1, 4, 8, 0, 1)
> +#define OP_TLBI_RIPAS2E1IS sys_insn(1, 4, 8, 0, 2)
> +#define OP_TLBI_IPAS2LE1IS sys_insn(1, 4, 8, 0, 5)
> +#define OP_TLBI_RIPAS2LE1IS sys_insn(1, 4, 8, 0, 6)
> +#define OP_TLBI_ALLE2OS sys_insn(1, 4, 8, 1, 0)
> +#define OP_TLBI_VAE2OS sys_insn(1, 4, 8, 1, 1)
> +#define OP_TLBI_ALLE1OS sys_insn(1, 4, 8, 1, 4)
> +#define OP_TLBI_VALE2OS sys_insn(1, 4, 8, 1, 5)
> +#define OP_TLBI_VMALLS12E1OS sys_insn(1, 4, 8, 1, 6)
> +#define OP_TLBI_RVAE2IS sys_insn(1, 4, 8, 2, 1)
> +#define OP_TLBI_RVALE2IS sys_insn(1, 4, 8, 2, 5)
> +#define OP_TLBI_ALLE2IS sys_insn(1, 4, 8, 3, 0)
> +#define OP_TLBI_VAE2IS sys_insn(1, 4, 8, 3, 1)
> +#define OP_TLBI_ALLE1IS sys_insn(1, 4, 8, 3, 4)
> +#define OP_TLBI_VALE2IS sys_insn(1, 4, 8, 3, 5)
> +#define OP_TLBI_VMALLS12E1IS sys_insn(1, 4, 8, 3, 6)
> +#define OP_TLBI_IPAS2E1OS sys_insn(1, 4, 8, 4, 0)
> +#define OP_TLBI_IPAS2E1 sys_insn(1, 4, 8, 4, 1)
> +#define OP_TLBI_RIPAS2E1 sys_insn(1, 4, 8, 4, 2)
> +#define OP_TLBI_RIPAS2E1OS sys_insn(1, 4, 8, 4, 3)
> +#define OP_TLBI_IPAS2LE1OS sys_insn(1, 4, 8, 4, 4)
> +#define OP_TLBI_IPAS2LE1 sys_insn(1, 4, 8, 4, 5)
> +#define OP_TLBI_RIPAS2LE1 sys_insn(1, 4, 8, 4, 6)
> +#define OP_TLBI_RIPAS2LE1OS sys_insn(1, 4, 8, 4, 7)
> +#define OP_TLBI_RVAE2OS sys_insn(1, 4, 8, 5, 1)
> +#define OP_TLBI_RVALE2OS sys_insn(1, 4, 8, 5, 5)
> +#define OP_TLBI_RVAE2 sys_insn(1, 4, 8, 6, 1)
> +#define OP_TLBI_RVALE2 sys_insn(1, 4, 8, 6, 5)
> +#define OP_TLBI_ALLE2 sys_insn(1, 4, 8, 7, 0)
> +#define OP_TLBI_VAE2 sys_insn(1, 4, 8, 7, 1)
> +#define OP_TLBI_ALLE1 sys_insn(1, 4, 8, 7, 4)
> +#define OP_TLBI_VALE2 sys_insn(1, 4, 8, 7, 5)
> +#define OP_TLBI_VMALLS12E1 sys_insn(1, 4, 8, 7, 6)
> +#define OP_TLBI_IPAS2E1ISNXS sys_insn(1, 4, 9, 0, 1)
> +#define OP_TLBI_RIPAS2E1ISNXS sys_insn(1, 4, 9, 0, 2)
> +#define OP_TLBI_IPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 5)
> +#define OP_TLBI_RIPAS2LE1ISNXS sys_insn(1, 4, 9, 0, 6)
> +#define OP_TLBI_ALLE2OSNXS sys_insn(1, 4, 9, 1, 0)
> +#define OP_TLBI_VAE2OSNXS sys_insn(1, 4, 9, 1, 1)
> +#define OP_TLBI_ALLE1OSNXS sys_insn(1, 4, 9, 1, 4)
> +#define OP_TLBI_VALE2OSNXS sys_insn(1, 4, 9, 1, 5)
> +#define OP_TLBI_VMALLS12E1OSNXS sys_insn(1, 4, 9, 1, 6)
> +#define OP_TLBI_RVAE2ISNXS sys_insn(1, 4, 9, 2, 1)
> +#define OP_TLBI_RVALE2ISNXS sys_insn(1, 4, 9, 2, 5)
> +#define OP_TLBI_ALLE2ISNXS sys_insn(1, 4, 9, 3, 0)
> +#define OP_TLBI_VAE2ISNXS sys_insn(1, 4, 9, 3, 1)
> +#define OP_TLBI_ALLE1ISNXS sys_insn(1, 4, 9, 3, 4)
> +#define OP_TLBI_VALE2ISNXS sys_insn(1, 4, 9, 3, 5)
> +#define OP_TLBI_VMALLS12E1ISNXS sys_insn(1, 4, 9, 3, 6)
> +#define OP_TLBI_IPAS2E1OSNXS sys_insn(1, 4, 9, 4, 0)
> +#define OP_TLBI_IPAS2E1NXS sys_insn(1, 4, 9, 4, 1)
> +#define OP_TLBI_RIPAS2E1NXS sys_insn(1, 4, 9, 4, 2)
> +#define OP_TLBI_RIPAS2E1OSNXS sys_insn(1, 4, 9, 4, 3)
> +#define OP_TLBI_IPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 4)
> +#define OP_TLBI_IPAS2LE1NXS sys_insn(1, 4, 9, 4, 5)
> +#define OP_TLBI_RIPAS2LE1NXS sys_insn(1, 4, 9, 4, 6)
> +#define OP_TLBI_RIPAS2LE1OSNXS sys_insn(1, 4, 9, 4, 7)
> +#define OP_TLBI_RVAE2OSNXS sys_insn(1, 4, 9, 5, 1)
> +#define OP_TLBI_RVALE2OSNXS sys_insn(1, 4, 9, 5, 5)
> +#define OP_TLBI_RVAE2NXS sys_insn(1, 4, 9, 6, 1)
> +#define OP_TLBI_RVALE2NXS sys_insn(1, 4, 9, 6, 5)
> +#define OP_TLBI_ALLE2NXS sys_insn(1, 4, 9, 7, 0)
> +#define OP_TLBI_VAE2NXS sys_insn(1, 4, 9, 7, 1)
> +#define OP_TLBI_ALLE1NXS sys_insn(1, 4, 9, 7, 4)
> +#define OP_TLBI_VALE2NXS sys_insn(1, 4, 9, 7, 5)
> +#define OP_TLBI_VMALLS12E1NXS sys_insn(1, 4, 9, 7, 6)
> +

As documented in DDI0487J.a.

Reviewed-by: Miguel Luis <miguel.luis at oracle.com>

FWIW, the remaining 34 TLBI instructions I’ve found in the same
document that are not in this patch had access ‘UNDEFINED’ from
Non-Secure.

Thanks
Miguel

> /* Common SCTLR_ELx flags. */
> #define SCTLR_ELx_ENTP2 (BIT(60))
> #define SCTLR_ELx_DSSBS (BIT(44))
> -- 
> 2.34.1
> 