[PATCH v2] arm64: gic: increase the number of IRQ descriptors

[Shanker Donthineni]

Hi Thomas & Marc,

On 1/10/23 16:36, Thomas Gleixner wrote:
> You can simply use a maple_tree for this.
> 
> static MTREE_INIT_EXT(sparse_irqs, MT_FLAGS_ALLOC_RANGE | MT_FLAGS_LOCK_EXTERN,
>                        sparse_irq_lock);
> 
> And the functions become:
> 
> static int irq_find_free_area(unsigned int from, unsigned int cnt)
> {
>          MA_STATE(mas, &sparse_irqs, 0, 0);
> 
>          if (mas_empty_area(&mas, from, MAX_SPARSE_IRQS, cnt))
>                  return -ENOSPC;
>          return mas.index;
> }
> 
> static unsigned int irq_find_next_irq(unsigned int offset)
> {
>          MA_STATE(mas, &sparse_irqs, offset, nr_irqs);
>          struct irq_desc *desc = mas_next(&mas, nr_irqs);
> 
>          return desc ? irq_desc_get_irq(desc) : nr_irqs;
> }
> 
> static int irq_insert_desc(irq, desc)
> {
>          MA_STATE(mas, @sparse_irqs, irq, irq);
> 
>          return mas_store_gfp(&mas, desc, GFP_KERNEL);
> }
> 
> static void irq_remove_desc(irq)
> {
>          MA_STATE(mas, @sparse_irqs, irq, irq);
> 
>          return mas_erase(&mas);
> }

Thank you for providing the necessary functions, they have been extremely
useful in getting started with implementing patches. However, I have encountered
corruption in the maple data structure within mtree_load() when multiple virtual
machines are being shut down simultaneously. To address this, I have added the
flag MT_FLAGS_USE_RCU to ensure safe concurrent access during reads and writes.

Please review patch series https://lore.kernel.org/all/20230130005725.3517597-1-sdonthineni@nvidia.com/

I have applied 6 patches from
  https://lore.kernel.org/all/20230109205336.3665937-2-surenb@google.com/#r
to resolve RCU mode issues. The patches were tested on an ARM64 server and
underwent several hours of evaluation with multiple virtual machines, yielding
positive results.


Thanks,
Shanker