[PATCH v4 2/5] dt-bindings: i2c: Add hpe,gxp-i2c

[Rob Herring]

On Wed, Jan 25, 2023 at 3:32 PM Hawkins, Nick <nick.hawkins at hpe.com> wrote:
>
> > > + hpe,sysreg:
> > > + $ref: /schemas/types.yaml#/definitions/phandle
> > > + description:
> > > + Phandle to the global status and enable interrupt registers shared
> > > + between each I2C engine controller instance. It enables the I2C
> > > + engine controller to act as both a master or slave by being able to
> > > + arm and respond to interrupts from its engine. Each bit in the
> > > + registers represent the respective bit position.
>
>
> > Each bit represents the bit position?
>
> Yes what I mean here is that bit 0 represents engine 0, bit 1 represents
> engine 1 and so on. I will reword this how you have below.
>
> > AIUI, each I2C instance has a bit in it needs to control. How does the
> > driver know what instance (and therefore the correct bit)? Typically you
> > would have a 2nd cell here with that information.
>
> We are currently using the memory area designated reg to determine
> which engine we are on.
>
> Here is a snippet from patch 1 of this patchset that introduces the driver:
> /* Use physical memory address to determine which I2C engine this is. */
> +       drvdata->engine = ((u32)drvdata->base & 0xf00) >> 8;
>
> This works because each engine is 0x100 apart.

Ah, that works fine then.

Reviewed-by: Rob Herring <robh at kernel.org>