[PATCH] ARM: dts: sun8i: a83t: bananapi-m3: describe SATA disk regulator

Samuel Holland samuel at sholland.org
Sat Jan 21 11:54:08 PST 2023


On 1/19/23 19:26, Andre Przywara wrote:
> The Bananapi-M3 has a SATA connector, driven by a USB-to-SATA bridge
> soldered on the board. The power for the SATA device is provided by a
> GPIO controlled regulator. Since the SATA device is behind USB, it has
> no DT node, so we never described this regulator. Instead U-Boot was
> turning this on in a rather hackish way, which we now want to get rid of.
> On top of that it seems fragile to leave this GPIO undescribed, as
> userland could claim it and turn the disk off.
> 
> Add a fixed regulator, controlled by the PD25 GPIO, and mark it as
> always-on. This would mimic the current situation, but in a safer way,
> and would allow U-Boot to drop the CONFIG_SATAPWR enable hack.
> 
> Signed-off-by: Andre Przywara <andre.przywara at arm.com>

Acked-by: Samuel Holland <samuel at sholland.org>

> ---
>  arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts | 15 +++++++++++++++
>  1 file changed, 15 insertions(+)
> 
> diff --git a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
> index 5a7e1bd5f8258..8d56b103f0630 100644
> --- a/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
> +++ b/arch/arm/boot/dts/sun8i-a83t-bananapi-m3.dts
> @@ -105,6 +105,21 @@ wifi_pwrseq: wifi_pwrseq {
>  		/* enables internal regulator and de-asserts reset */
>  		reset-gpios = <&r_pio 0 2 GPIO_ACTIVE_LOW>; /* PL2 WL-PMU-EN */
>  	};
> +
> +	/*
> +	 * Power supply for the SATA disk, behind a USB-SATA bridge.
> +	 * Since it is a USB device, there is no consumer in the DT, so we
> +	 * have to keep this always on.
> +	 */
> +	regulator-sata-disk-pwr {
> +		compatible = "regulator-fixed";
> +		regulator-name = "sata-disk-pwr";
> +		regulator-min-microvolt = <5000000>;
> +		regulator-max-microvolt = <5000000>;
> +		regulator-always-on;
> +		enable-active-high;
> +		gpio = <&pio 3 25 GPIO_ACTIVE_HIGH>; /* PD25 */
> +	};
>  };
>  
>  &cpu0 {




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