[PATCH v2] arm64: Avoid repeated AA64MMFR1_EL1 register read on pagefault path

[Will Deacon]

On Mon, Jan 16, 2023 at 05:41:35PM -0300, Gabriel Krisman Bertazi wrote:
> Gabriel Krisman Bertazi <krisman at suse.de> writes:
> 
> > Accessing AA64MMFR1_EL1 is expensive in KVM guests, since it is emulated
> > in the hypervisor.  In fact, ARM documentation mentions some feature
> > registers are not supposed to be accessed frequently by the OS, and
> > therefore should be emulated for guests [1].
> >
> > Commit 0388f9c74330 ("arm64: mm: Implement
> > arch_wants_old_prefaulted_pte()") introduced a read of this register in
> > the page fault path.  But, even when the feature of setting faultaround
> > pages with the old flag is disabled for a given cpu, we are still paying
> > the cost of checking the register on every pagefault. This results in an
> > explosion of vmexit events in KVM guests, which directly impacts the
> > performance of virtualized workloads.  For instance, running kernbench
> > yields a 15% increase in system time solely due to the increased vmexit
> > cycles.
> >
> > This patch avoids the extra cost by using the sanitized cached value.
> > It should be safe to do so, since this register mustn't change for a
> > given cpu.
> >
> > [1] https://developer.arm.com/-/media/Arm%20Developer%20Community/PDF/Learn%20the%20Architecture/Armv8-A%20virtualization.pdf?revision=a765a7df-1a00-434d-b241-357bfda2dd31
> >
> > Signed-off-by: Gabriel Krisman Bertazi <krisman at suse.de>
> 
> Hi,
> 
> Considering the performance impact on kvm guests, unless someone
> opposes, can we get this queued already for -rc5?

Given this has been the case since v5.12 afaict and it's not a correctness
issue, I was thinking we could queue this for 6.3?

Will