[PATCH 1/3] arm64: dts: mediatek: Introduce MT8195 LAPTOP and IOT's USB configurations

[Krzysztof Kozlowski]

On 05/01/2023 10:28, Macpaul Lin wrote:
> Introduce the split MT8195 laptop and iot USB configurations.
> The hardware specifications for LAPTOP devices is different from IOT
> devices. The major differences include some hardware constrains for
> dual-role switch for USB controllers in different configurations,
> especially for power management and other control flows as well.
> 
> Here are some hardware specifiction differences listed:
>   1. LAPTOP (Cherry Tomato boards) don't support USB gadget (device mode).
>   2. IOT devices must support multiple gadget devices and host mode.
>   3. Dual-role switch is not fully supported. Only USB PORT0 support
>      dual-role switch.
>   4. Power management is designed in primary and secondary dominator.
>      For a dual-role port, the device controller is the primary controller
>      for power management; while the host controller is the secondary.
>      LAPTOP devices should remove device nodes for avoiding abnormal
>      behavior.
> 
> This modifcation is to add USB configurations "mt8195-laptop-usb.dtsi"
> for LAPTOP devices, and add "mt8195-iot-usb.dtsi" for IOT devices.
> 
> To remove common USB configurations for mt8195.dtsi and switch includes
> dtsi these new files for the boards will come in next patch.
> 
> Signed-off-by: Macpaul Lin <macpaul.lin at mediatek.com>
> ---
>  .../boot/dts/mediatek/mt8195-iot-usb.dtsi     | 122 ++++++++++++++++++
>  .../boot/dts/mediatek/mt8195-laptop-usb.dtsi  | 102 +++++++++++++++
>  2 files changed, 224 insertions(+)
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-iot-usb.dtsi
>  create mode 100644 arch/arm64/boot/dts/mediatek/mt8195-laptop-usb.dtsi
> 
> diff --git a/arch/arm64/boot/dts/mediatek/mt8195-iot-usb.dtsi b/arch/arm64/boot/dts/mediatek/mt8195-iot-usb.dtsi
> new file mode 100644
> index 000000000000..f9bd79542044
> --- /dev/null
> +++ b/arch/arm64/boot/dts/mediatek/mt8195-iot-usb.dtsi
> @@ -0,0 +1,122 @@
> +// SPDX-License-Identifier: (GPL-2.0 OR MIT)
> +/*
> + * Copyright (C) 2022 MediaTek Inc.
> + */
> +
> +#include "mt8195.dtsi"
> +
> +/ {
> +	soc {
> +		ssusb: ssusb at 11200000 {

Node name: usb

> +			compatible ="mediatek,mt8183-mtu3", "mediatek,mtu3";
> +			reg = <0 0x11201000 0 0x2dff>,
> +			      <0 0x11203e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts = <GIC_SPI 128 IRQ_TYPE_LEVEL_HIGH 0>;
> +			phys = <&u2port0 PHY_TYPE_USB2>,
> +			       <&u3port0 PHY_TYPE_USB3>;
> +			clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
> +				 <&topckgen CLK_TOP_SSUSB_REF>,
> +				 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>;
> +			clock-names = "sys_ck", "ref_ck", "mcu_ck";
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +			status = "disabled";
> +
> +			xhci0: xhci at 11200000 {
> +				compatible = "mediatek,mt8195-xhci",
> +					     "mediatek,mtk-xhci";
> +				reg = <0 0x11200000 0 0x1000>;
> +				reg-names = "mac";
> +				interrupts = <GIC_SPI 129 IRQ_TYPE_LEVEL_HIGH 0>;
> +				assigned-clocks = <&topckgen CLK_TOP_USB_TOP>,
> +						  <&topckgen CLK_TOP_SSUSB_XHCI>;
> +				assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> +							 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +				clocks = <&infracfg_ao CLK_INFRA_AO_SSUSB>,
> +					 <&infracfg_ao CLK_INFRA_AO_SSUSB_XHCI>,
> +					 <&topckgen CLK_TOP_SSUSB_REF>,
> +					 <&apmixedsys CLK_APMIXED_USB1PLL>;
> +				clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
> +				status = "disabled";
> +			};
> +		};
> +
> +		xhci1: xhci1 at 11290000 {

Node names should be generic, so just "xhci"
https://devicetree-specification.readthedocs.io/en/latest/chapter2-devicetree-basics.html#generic-names-recommendation

> +			compatible = "mediatek,mt8195-xhci",
> +				     "mediatek,mtk-xhci";
> +			reg = <0 0x11290000 0 0x1000>,
> +			      <0 0x11293e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts = <GIC_SPI 530 IRQ_TYPE_LEVEL_HIGH 0>;
> +			phys = <&u2port1 PHY_TYPE_USB2>,
> +			       <&u3port1 PHY_TYPE_USB3>;
> +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_1P>,
> +					  <&topckgen CLK_TOP_SSUSB_XHCI_1P>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> +						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_1P_BUS>,
> +				 <&pericfg_ao CLK_PERI_AO_SSUSB_1P_XHCI>,
> +				 <&topckgen CLK_TOP_SSUSB_P1_REF>,
> +				 <&apmixedsys CLK_APMIXED_USB1PLL>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck", "mcu_ck";
> +			status = "disabled";
> +		};
> +
> +		ssusb1: usb1 at 112a1000 {

usb

> +			compatible = "mediatek,mt8183-mtu3", "mediatek,mtu3";
> +			reg = <0 0x112a1000 0 0x2dff>,
> +				  <0 0x112a3e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts = <GIC_SPI 532 IRQ_TYPE_LEVEL_HIGH 0>;
> +			phys = <&u2port2 PHY_TYPE_USB2>;
> +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_2P>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_BUS>,
> +				 <&topckgen CLK_TOP_SSUSB_P2_REF>,
> +				 <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
> +			clock-names = "sys_ck", "ref_ck", "mcu_ck";
> +			mediatek,syscon-wakeup = <&pericfg 0x400 4>;
> +			#address-cells = <2>;
> +			#size-cells = <2>;
> +			ranges;
> +			status = "disabled";
> +
> +			xhci2: xhci2 at 112a0000 {

xhci

> +				compatible = "mediatek,mt8195-xhci","mediatek,mtk-xhci";
> +				reg = <0 0x112a0000 0 0x1000>;
> +				reg-names = "mac";
> +				interrupts-extended = <&gic GIC_SPI 533 IRQ_TYPE_LEVEL_HIGH 0>,
> +					      <&pio 220 IRQ_TYPE_EDGE_FALLING>;
> +				assigned-clocks = <&topckgen CLK_TOP_SSUSB_XHCI_2P>;
> +				assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +				clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_2P_XHCI>;
> +				clock-names = "sys_ck";
> +				status = "disabled";
> +			};
> +		};
> +
> +		xhci3: xhci3 at 112b0000 {

xhci
> +			compatible = "mediatek,mt8195-xhci",
> +				     "mediatek,mtk-xhci";
> +			reg = <0 0x112b0000 0 0x1000>,
> +			      <0 0x112b3e00 0 0x0100>;
> +			reg-names = "mac", "ippc";
> +			interrupts = <GIC_SPI 536 IRQ_TYPE_LEVEL_HIGH 0>;
> +			phys = <&u2port3 PHY_TYPE_USB2>;
> +			assigned-clocks = <&topckgen CLK_TOP_USB_TOP_3P>,
> +					  <&topckgen CLK_TOP_SSUSB_XHCI_3P>;
> +			assigned-clock-parents = <&topckgen CLK_TOP_UNIVPLL_D5_D4>,
> +						 <&topckgen CLK_TOP_UNIVPLL_D5_D4>;
> +			clocks = <&pericfg_ao CLK_PERI_AO_SSUSB_3P_BUS>,
> +				 <&pericfg_ao CLK_PERI_AO_SSUSB_3P_XHCI>,
> +				 <&topckgen CLK_TOP_SSUSB_P3_REF>;
> +			clock-names = "sys_ck", "xhci_ck", "ref_ck";
> +			mediatek,syscon-wakeup = <&pericfg 0x400 106>;
> +			wakeup-source;
> +			usb2-lpm-disable;
> +			status = "disabled";
> +		};


Best regards,
Krzysztof