[PATCH v2] phy: stm32-usphyc: add 200 to 300 us delay to fix timeout on some machines
Fabrice Gasnier
fabrice.gasnier at foss.st.com
Tue Feb 28 09:28:21 PST 2023
On 2/27/23 16:13, Michael Grzeschik wrote:
> An minimum udelay of 200 us seems to be necessary on some machines. After
> the setup of the pll, which needs about 100 us to be locked there seem
> to be additional 100 us to get the phy really functional. Without this
> delay the usb runs not functional. With this additional short udelay
> this issue was not reported again.
>
> Signed-off-by: Michael Grzeschik <m.grzeschik at pengutronix.de>
>
Hi Michael,
Thank you for the updates,
Fell free to add my:
Reviewed-by: Fabrice Gasnier <fabrice.gasnier at foss.st.com>
Best Regards,
Fabrice
> ---
> v1 -> v2: - changed the mdelay to udelay_range(200, 300), like suggested by fabrice
> - moved the delay to pll enable so it will only be triggered once
>
> drivers/phy/st/phy-stm32-usbphyc.c | 3 +++
> 1 file changed, 3 insertions(+)
>
> diff --git a/drivers/phy/st/phy-stm32-usbphyc.c b/drivers/phy/st/phy-stm32-usbphyc.c
> index 5bb9647b078f12..dd469f57fba7eb 100644
> --- a/drivers/phy/st/phy-stm32-usbphyc.c
> +++ b/drivers/phy/st/phy-stm32-usbphyc.c
> @@ -317,6 +317,9 @@ static int stm32_usbphyc_pll_enable(struct stm32_usbphyc *usbphyc)
>
> stm32_usbphyc_set_bits(pll_reg, PLLEN);
>
> + /* Wait for maximum lock time */
> + usleep_range(200, 300);
> +
> return 0;
>
> reg_disable:
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