[PATCH v3 0/7] PCI: dwc: Add support for Marvell AC5 SoC

[Bjorn Helgaas]

On Thu, Feb 23, 2023 at 08:05:24PM +0200, Elad Nachman wrote:
> From: Elad Nachman <enachman at marvell.com>
> 
> Add support for AC5 SoC with MSI and in message emulated legacy mode.
> There are differences in the registers addresses, blocks, DDR location
> for coherent DMA allocation and additional implementation specific registers.
> In addition, support cases of older Designware IP (Armada 7020) which supports
> above 4GB PCIe physical memory window by use of device tree.
> ...

> Elad Nachman (4):
>   dt-bindings: PCI: dwc: add DMA, region mask bits
>   PCI: dwc: support AC5 Legacy PCIe interrupts
>   PCI: dwc: Introduce Configurable DMA mask
>   PCI: dwc: Introduce region limit from DT
> 
> Raz Adashi (1):
>   PCI: armada8k: Add AC5 SoC support
> 
> Vadym Kochan (1):
>   dt-bindings: PCI: armada8k: Add compatible string for AC5 SoC
> 
> Yuval Shaia (1):
>   PCI: armada8k: Add MSI support for AC5 SoC

Capitalize subject consistently.  Use consistent driver tags.  Use
parallel sentence structure.

s/add DMA/Add DMA/
s/PCI: dwc: support/PCI: armada8k: Support/
  (this particular patch only affects armada8k, so don't label it "dwc")
s/support/Support/
s/Configurable/configurable/
s/Add MSI support for AC5 SoC/Add AC5 MSI support/
  (parallel to "Add AC5 SoC support")

The PCIe spec doesn't really use "legacy" when defining the interrupt
model.  I think you're referring to INTx, which it *does* use and is
more specific.  If so, please say "INTx interrupts" instead of "legacy
PCIe interrupts".