[PATCH 02/16] arm64: Add HAS_ECV_CNTPOFF capability

[Marc Zyngier]

On Wed, 22 Feb 2023 04:30:00 +0000,
Reiji Watanabe <reijiw at google.com> wrote:
> 
> Hi Marc,
> 
> On Thu, Feb 16, 2023 at 6:21 AM Marc Zyngier <maz at kernel.org> wrote:
> >
> > Add the probing code for the FEAT_ECV variant that implements CNTPOFF_EL2.
> > Why is it optional is a mystery, but let's try and detect it.
> >
> > Signed-off-by: Marc Zyngier <maz at kernel.org>
> > ---
> >  arch/arm64/kernel/cpufeature.c | 11 +++++++++++
> >  arch/arm64/tools/cpucaps       |  1 +
> >  2 files changed, 12 insertions(+)
> >
> > diff --git a/arch/arm64/kernel/cpufeature.c b/arch/arm64/kernel/cpufeature.c
> > index 23bd2a926b74..36852f96898d 100644
> > --- a/arch/arm64/kernel/cpufeature.c
> > +++ b/arch/arm64/kernel/cpufeature.c
> > @@ -2186,6 +2186,17 @@ static const struct arm64_cpu_capabilities arm64_features[] = {
> >                 .sign = FTR_UNSIGNED,
> >                 .min_field_value = 1,
> >         },
> > +       {
> > +               .desc = "Enhanced Counter Virtualization (CNTPOFF)",
> > +               .capability = ARM64_HAS_ECV_CNTPOFF,
> > +               .type = ARM64_CPUCAP_SYSTEM_FEATURE,
> > +               .matches = has_cpuid_feature,
> > +               .sys_reg = SYS_ID_AA64MMFR0_EL1,
> > +               .field_pos = ID_AA64MMFR0_EL1_ECV_SHIFT,
> > +               .field_width = 4,
> > +               .sign = FTR_UNSIGNED,
> > +               .min_field_value = 2,
> 
> Nit: You might want to use ID_AA64MMFR0_EL1_ECV_CNTPOFF (instead of 2) ?

Ah, of course! ;-)

> Reviewed-by: Reiji Watanabe <reijiw at google.com>

Thanks,

	M.

-- 
Without deviation from the norm, progress is not possible.