[RFC PATCH 0/3] arm64: errata: Disable FWB on parts with non-ARM interconnects

[James Morse]

Hello!

When stage1 translation is disabled, the SCTRL_E1.I bit controls the
attributes used for instruction fetch, one of the options results in a
non-cacheable access. A whole host of CPUs missed the FWB override
in this case, meaning a KVM guest could fetch stale/junk data instead of
instructions.

The workaround is to disable FWB, and do the required cache maintenance
instead.

The good news is, this isn't a problem for systems using Arm's
interconnect IP. The bad news is: linux can't know this. Arm knows of
at least one platform that is affected by this erratum.


This series adds support for the 'Errata Management Firmware Interface', [0]
and queries that to determine if the CPU is affected or not.

Unfortunately, no-one has firmware that supports this new interface yet,
and the least surprising thing to do is to enable the workaround by default,
meaning FWB is disabled on all these cores, even for unaffected platforms.
Platforms that are not-affected can either take a firmware-update to support
the interface, or if the kernel they run will only run on hardware that is
unaffected, disable the workaround at build time.

The trusted firmware series to implement the interface has not yet been
posted. I'll include a link once it is.

This series is an RFC as I anticipate a wider discussion around how we add
workaround that depend on firmware for detection.

The SDEN documents that describe this are:
Cortex-A78:
https://developer.arm.com/documentation/SDEN1401784/1800/?lang=en
Cortex-A78C:
https://developer.arm.com/documentation/SDEN1707916/1300/?lang=en
https://developer.arm.com/documentation/SDEN2004089/0700/?lang=en
(yes, there are two!)
Cortex-A710:
https://developer.arm.com/documentation/SDEN1775101/1500/?lang=en
Cortex-X1:
https://developer.arm.com/documentation/SDEN1401782/1800/?lang=en
Cortex-X2:
https://developer.arm.com/documentation/SDEN1775100/1500/?lang=en
Cortex-X3:
https://developer.arm.com/documentation/SDEN2055130/1000/?lang=en
Cortex-V1:
https://developer.arm.com/documentation/SDEN1401781/1600/?lang=en
Cortex-V2:
https://developer.arm.com/documentation/SDEN2332927/0500/?lang=en
Cortex-N2:
https://developer.arm.com/documentation/SDEN1982442/1200/?lang=en

Thanks,

James

[0] https://developer.arm.com/documentation/den0100/1-0/?lang=en

James Morse (3):
  firmware: smccc: Add support for erratum discovery API
  arm64: cputype: Add new part numbers for Cortex-X3, and Neoverse-V2
  arm64: errata: Disable FWB on parts with non-ARM interconnects

 Documentation/arm64/silicon-errata.rst | 18 ++++++
 arch/arm64/Kconfig                     | 27 +++++++++
 arch/arm64/include/asm/cputype.h       |  4 ++
 arch/arm64/kernel/cpufeature.c         | 77 ++++++++++++++++++++++++-
 drivers/firmware/smccc/Kconfig         |  8 +++
 drivers/firmware/smccc/Makefile        |  1 +
 drivers/firmware/smccc/em.c            | 78 ++++++++++++++++++++++++++
 include/linux/arm-smccc.h              | 28 +++++++++
 8 files changed, 240 insertions(+), 1 deletion(-)
 create mode 100644 drivers/firmware/smccc/em.c

-- 
2.30.2