[PATCH V4 4/9] i2c: xiic: Add wait for FIFO empty in send_tx

[Wolfram Sang]

On Thu, Feb 02, 2023 at 03:11:33PM +0530, Manikanta Guntupalli wrote:
> From: Raviteja Narayanam <raviteja.narayanam at xilinx.com>
> 
> If the tx_half_empty interrupt comes first instead of tx_empty,
> STOP bit is generated even before all the bytes are transmitted
> out on the bus.
> STOP bit should be sent only after all the bytes in the FIFO are
> transmitted out of the FIFO. So wait until FIFO is empty before sending
> the STOP bit.
> 
> Signed-off-by: Raviteja Narayanam <raviteja.narayanam at xilinx.com>
> Signed-off-by: Manikanta Guntupalli <manikanta.guntupalli at amd.com>
> Acked-by: Michal Simek <michal.simek at amd.com>

Applied to for-next, thanks!

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