[PATCH 2/9] net: ethernet: mtk_eth_soc: set MDIO bus clock frequency

[Andrew Lunn]

>  static int mtk_mdio_init(struct mtk_eth *eth)
>  {
>  	struct device_node *mii_np;
> +	int clk = 25000000, max_clk = 2500000, divider = 1;
>  	int ret;
> +	u32 val;

Reverse Christmas tree please.

> +
> +	if (!of_property_read_u32(mii_np, "clock-frequency", &val))
> +		max_clk = val;
> +
> +	while (clk / divider > max_clk) {
> +		if (divider >= 63)
> +			break;
> +
> +		divider++;
> +	};

Please add some range checks here. Return -EINVAL if val > max_clock.
Also, if divider = 63 indicating the requested clock is too slow.

> +
> +	val = mtk_r32(eth, MTK_PPSC);
> +	val |= PPSC_MDC_TURBO;
> +	mtk_w32(eth, val, MTK_PPSC);
> +
> +	/* Configure MDC Divider */
> +	val = mtk_r32(eth, MTK_PPSC);
> +	val &= ~PPSC_MDC_CFG;
> +	val |= FIELD_PREP(PPSC_MDC_CFG, divider);
> +	mtk_w32(eth, val, MTK_PPSC);

Can these two writes to MTK_PPSC be combined into one? 

val |= FIELD_PREP(PPSC_MDC_CFG, divider) | PPSC_MDC_TURBO;

    Andrew