About the Naneng combo phy differences in 3568/3588.

[Qu Wenruo]

Hi Sebastaian and YiFeng,

Thank you very much for the contribution on upstreaming the RK3568 SoC 
and the incoming RK3588 SoC.

During my (uneducated) attempt to add RK3588 comb phy to upstream, I 
found something unsure and the data-sheet would be way better to make 
the code meet the upstream standard (Either Chinese or English version 
is fine to me):

- rk3568 and rk3588 grcfgs have differences starting at con0_for_sata
   Otherwise members before that one are sharing the same values.

   I guess it's just some expected value changes, but just want to make
   sure it's indeed the case.

- SCC downward spread spectrum only applied to 3568 combo phy
   But not for rk3588. Is it due to some EMI changes?

- Needs data sheet for various register values
   The downstream code involves the following registers for rk3388 combo
   phy for PCIE mode:

   * PHYREG30 (0x74)
     For "gate_tx_pck_sel length selection for L1SS".
     And I'm wondering if ASPM is involved in the downstream kernel crash
     during PCIE initialization.

   * PHYREG28 (0x6c)
     For "rx_trim: PLL LPF C1 85pf R1 1.25kohm."
     (Sorry, I can only understand the last 3 words)

   * PHYREG10 (0x28) extra bits
   * PHYREG11 (0x2C) extra bits
   * PHYREG14 (0x34) extra bits
     For the "su_trim: T3" for PCIE initialization and with extra
     refclock.

   * PHYREG26 (0x64)
     For the ".force_det_out" setting.

I really hope I can help on upstreaming the PCIE controller, so I can 
run upstream kernels on my Rock5B boards.
(Since the R8125 ethernet controller is on that combo phy)

Thanks,
Qu