[PATCH] phy: stm32-usphyc: add mdelay(1) to fix timeout on some machines
Fabrice Gasnier
fabrice.gasnier at foss.st.com
Wed Feb 1 08:20:11 PST 2023
On 1/24/23 21:45, Michael Grzeschik wrote:
> An mdelay of 1 seems to be necessary on some machines, since
Hi Michael,
Could you precise on which board ?
> the monsel status does not seem to be accurate. On rare occasions just
> working with the phy after this pll check lead to no functional usb.
Could you elaborate on the symptoms (provide some error logs) ?
> With this short mdelay this issue was not reported again.
>
> Signed-off-by: Michael Grzeschik <m.grzeschik at pengutronix.de>
> ---
> drivers/phy/st/phy-stm32-usbphyc.c | 9 +++++++++
> 1 file changed, 9 insertions(+)
>
> diff --git a/drivers/phy/st/phy-stm32-usbphyc.c b/drivers/phy/st/phy-stm32-usbphyc.c
> index 5bb9647b078f12..c452a0caceb9fa 100644
> --- a/drivers/phy/st/phy-stm32-usbphyc.c
> +++ b/drivers/phy/st/phy-stm32-usbphyc.c
> @@ -353,6 +353,15 @@ static int stm32_usbphyc_phy_init(struct phy *phy)
> goto pll_disable;
> }
>
> + /* This mdelay seems to be necessary on some machines, since the
> + * monsel status does not seem to be accurate. On rare occasions
> + * just working with the phy after this pll check the usb
> + * peripheral (e.g. on the dwc2) run into timeout issues and
> + * leading to no functional usb. With this short mdelay this
> + * issue was not reported again.
> + */
> + mdelay(1);
> +
The USBPHYC provides two PHY interfaces:
- PHY port#1 is for USBH
- PHY port#2 can be assigned to USBH or DWC2.
Adding some delay here, we'll hit twice this penalty (e.g. for USBH +
DWC2 or dual USBH) on all MP1 (MP13 & MP15) platforms.
Could you try to narrow down the issue by adding some debug log in:
- stm32_usbphyc_phy_init
- stm32_usbphyc_clk48_prepare
Best Regards,
Fabrice
> usbphyc_phy->active = true;
>
> return 0;
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