[PATCH] irqchip/irq-brcmstb-l2: add write memory barrier before exit

[Florian Fainelli]

On 12/20/2023 8:32 PM, Doug Berger wrote:
> It was observed on Broadcom devices that use GIC v3 architecture
> L1 interrupt controllers as the parent of brcmstb-l2 interrupt
> controllers that the deactivation of the parent irq could happen
> before the brcmstb-l2 deasserted its output. This would lead the
> GIC to reactivate the irq only to find that no L2 interrupt was
> pending. The result was a spurious interrupt invoking the
> handle_bad_irq() with its associated messaging. While this did
> not create a functional problem it is a waste of cycles.
> 
> The hazard exists because the memory mapped bus writes to the
> brcmstb-l2 registers are buffered and the GIC v3 architecture
> uses a very efficient system register write to deactivate the
> interrupt. This commit adds a write memory barrier prior to
> invoking chained_irq_exit() to introduce a dsb(st) on those
> systems to ensure the system register write cannot be executed
> until the memory mapped writes are visible to the system.
> 
> Signed-off-by: Doug Berger <opendmb at gmail.com>

Acked-by: Florian Fainelli <florian.fainelli at broadcom.com>

I would be even keen on slapping a:

Fixes: 7f646e92766e ("irqchip: brcmstb-l2: Add Broadcom Set Top Box 
Level-2 interrupt controller")

Thanks Doug!
-- 
Florian
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