[PATCH 2/3] arm64: dts: ti: k3-j721s2-main: Add Itap Delay Value For DDR50 speed mode

[Judith Mendez]

Hi Bhavya,

On 12/1/23 2:20 AM, Bhavya Kapoor wrote:
> DDR50 speed mode is enabled for MMCSD in J721s2 but its Itap Delay
> Value is not present in the device tree. Thus, add Itap Delay Value
> for MMCSD High Speed DDR which is DDR50 speed mode for J721s2 SoC
> according to datasheet for J721s2.
> 
> [+] Refer to : section 7.10.5.17.2 MMC1/2 - SD/SDIO Interface,  in
> 	J721s2 datasheet
> - https://www.ti.com/lit/ds/symlink/tda4vl-q1.pdf
> 

LGTM

Reviewed-by: Judith Mendez <jm at ti.com>

> Signed-off-by: Bhavya Kapoor <b-kapoor at ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> index b03731b53a26..e1255956288b 100644
> --- a/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j721s2-main.dtsi
> @@ -766,6 +766,7 @@ main_sdhci1: mmc at 4fb0000 {
>   		ti,itap-del-sel-sd-hs = <0x0>;
>   		ti,itap-del-sel-sdr12 = <0x0>;
>   		ti,itap-del-sel-sdr25 = <0x0>;
> +		ti,itap-del-sel-ddr50 = <0x2>;
>   		ti,clkbuf-sel = <0x7>;
>   		ti,trm-icp = <0x8>;
>   		dma-coherent;

~ Judith