[PATCH 1/3] arm64: dts: ti: k3-j7200-main: Add Itap Delay Value For DDR52 speed mode

[Judith Mendez]

Hi Bhavya,

On 12/1/23 2:20 AM, Bhavya Kapoor wrote:
> DDR52 speed mode is enabled for eMMC in J7200 but its Itap Delay Value
> is not present in the device tree. Thus, add Itap Delay Value for eMMC
> High Speed DDR which is DDR52 speed mode for J7200 SoC according to
> datasheet for J7200.
> 
> [+] Refer to : section 7.9.5.16.1 MMCSD0 - eMMC Interface,  in
> 	J7200 datasheet
> - https://www.ti.com/lit/ds/symlink/dra821u-q1.pdf
> 

LGTM

Reviewed-by: Judith Mendez <jm at ti.com>

> Signed-off-by: Bhavya Kapoor <b-kapoor at ti.com>
> ---
>   arch/arm64/boot/dts/ti/k3-j7200-main.dtsi | 1 +
>   1 file changed, 1 insertion(+)
> 
> diff --git a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> index 264913f83287..39ce465c8e00 100644
> --- a/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> +++ b/arch/arm64/boot/dts/ti/k3-j7200-main.dtsi
> @@ -647,6 +647,7 @@ main_sdhci0: mmc at 4f80000 {
>   		ti,otap-del-sel-hs400 = <0x5>;
>   		ti,itap-del-sel-legacy = <0x10>;
>   		ti,itap-del-sel-mmc-hs = <0xa>;
> +		ti,itap-del-sel-ddr52 = <0x3>;
>   		ti,strobe-sel = <0x77>;
>   		ti,clkbuf-sel = <0x7>;
>   		ti,trm-icp = <0x8>;

~ Judith