[PATCH v4 21/28] KVM: arm64: nv: Add trap forwarding for HFGITR_EL2
Jing Zhang
jingzhangos at google.com
Tue Aug 15 15:55:39 PDT 2023
Hi Marc,
On Tue, Aug 15, 2023 at 11:47 AM Marc Zyngier <maz at kernel.org> wrote:
>
> Similarly, implement the trap forwarding for instructions affected
> by HFGITR_EL2.
>
> Note that the TLBI*nXS instructions should be affected by HCRX_EL2,
> which will be dealt with down the line. Also, ERET* and SVC traps
> are handled separately.
>
> Reviewed-by: Eric Auger <eric.auger at redhat.com>
> Signed-off-by: Marc Zyngier <maz at kernel.org>
> ---
> arch/arm64/include/asm/kvm_arm.h | 4 ++
> arch/arm64/kvm/emulate-nested.c | 109 +++++++++++++++++++++++++++++++
> 2 files changed, 113 insertions(+)
>
> diff --git a/arch/arm64/include/asm/kvm_arm.h b/arch/arm64/include/asm/kvm_arm.h
> index 85908aa18908..809bc86acefd 100644
> --- a/arch/arm64/include/asm/kvm_arm.h
> +++ b/arch/arm64/include/asm/kvm_arm.h
> @@ -354,6 +354,10 @@
> #define __HFGWTR_EL2_MASK GENMASK(49, 0)
> #define __HFGWTR_EL2_nMASK (GENMASK(55, 54) | BIT(50))
>
> +#define __HFGITR_EL2_RES0 GENMASK(63, 57)
> +#define __HFGITR_EL2_MASK GENMASK(54, 0)
> +#define __HFGITR_EL2_nMASK GENMASK(56, 55)
> +
> /* Hyp Prefetch Fault Address Register (HPFAR/HDFAR) */
> #define HPFAR_MASK (~UL(0xf))
> /*
> diff --git a/arch/arm64/kvm/emulate-nested.c b/arch/arm64/kvm/emulate-nested.c
> index 0e34797515b6..a1a7792db412 100644
> --- a/arch/arm64/kvm/emulate-nested.c
> +++ b/arch/arm64/kvm/emulate-nested.c
> @@ -939,6 +939,7 @@ static DEFINE_XARRAY(sr_forward_xa);
> enum fgt_group_id {
> __NO_FGT_GROUP__,
> HFGxTR_GROUP,
> + HFGITR_GROUP,
>
> /* Must be last */
> __NR_FGT_GROUP_IDS__
> @@ -1020,6 +1021,110 @@ static const struct encoding_to_trap_config encoding_to_fgt[] __initconst = {
> SR_FGT(SYS_AIDR_EL1, HFGxTR, AIDR_EL1, 1),
> SR_FGT(SYS_AFSR1_EL1, HFGxTR, AFSR1_EL1, 1),
> SR_FGT(SYS_AFSR0_EL1, HFGxTR, AFSR0_EL1, 1),
> + /* HFGITR_EL2 */
> + SR_FGT(OP_BRB_IALL, HFGITR, nBRBIALL, 0),
> + SR_FGT(OP_BRB_INJ, HFGITR, nBRBINJ, 0),
> + SR_FGT(SYS_DC_CVAC, HFGITR, DCCVAC, 1),
> + SR_FGT(SYS_DC_CGVAC, HFGITR, DCCVAC, 1),
> + SR_FGT(SYS_DC_CGDVAC, HFGITR, DCCVAC, 1),
> + SR_FGT(OP_CPP_RCTX, HFGITR, CPPRCTX, 1),
> + SR_FGT(OP_DVP_RCTX, HFGITR, DVPRCTX, 1),
> + SR_FGT(OP_CFP_RCTX, HFGITR, CFPRCTX, 1),
> + SR_FGT(OP_TLBI_VAALE1, HFGITR, TLBIVAALE1, 1),
> + SR_FGT(OP_TLBI_VALE1, HFGITR, TLBIVALE1, 1),
> + SR_FGT(OP_TLBI_VAAE1, HFGITR, TLBIVAAE1, 1),
> + SR_FGT(OP_TLBI_ASIDE1, HFGITR, TLBIASIDE1, 1),
> + SR_FGT(OP_TLBI_VAE1, HFGITR, TLBIVAE1, 1),
> + SR_FGT(OP_TLBI_VMALLE1, HFGITR, TLBIVMALLE1, 1),
> + SR_FGT(OP_TLBI_RVAALE1, HFGITR, TLBIRVAALE1, 1),
> + SR_FGT(OP_TLBI_RVALE1, HFGITR, TLBIRVALE1, 1),
> + SR_FGT(OP_TLBI_RVAAE1, HFGITR, TLBIRVAAE1, 1),
> + SR_FGT(OP_TLBI_RVAE1, HFGITR, TLBIRVAE1, 1),
> + SR_FGT(OP_TLBI_RVAALE1IS, HFGITR, TLBIRVAALE1IS, 1),
> + SR_FGT(OP_TLBI_RVALE1IS, HFGITR, TLBIRVALE1IS, 1),
> + SR_FGT(OP_TLBI_RVAAE1IS, HFGITR, TLBIRVAAE1IS, 1),
> + SR_FGT(OP_TLBI_RVAE1IS, HFGITR, TLBIRVAE1IS, 1),
> + SR_FGT(OP_TLBI_VAALE1IS, HFGITR, TLBIVAALE1IS, 1),
> + SR_FGT(OP_TLBI_VALE1IS, HFGITR, TLBIVALE1IS, 1),
> + SR_FGT(OP_TLBI_VAAE1IS, HFGITR, TLBIVAAE1IS, 1),
> + SR_FGT(OP_TLBI_ASIDE1IS, HFGITR, TLBIASIDE1IS, 1),
> + SR_FGT(OP_TLBI_VAE1IS, HFGITR, TLBIVAE1IS, 1),
> + SR_FGT(OP_TLBI_VMALLE1IS, HFGITR, TLBIVMALLE1IS, 1),
> + SR_FGT(OP_TLBI_RVAALE1OS, HFGITR, TLBIRVAALE1OS, 1),
> + SR_FGT(OP_TLBI_RVALE1OS, HFGITR, TLBIRVALE1OS, 1),
> + SR_FGT(OP_TLBI_RVAAE1OS, HFGITR, TLBIRVAAE1OS, 1),
> + SR_FGT(OP_TLBI_RVAE1OS, HFGITR, TLBIRVAE1OS, 1),
> + SR_FGT(OP_TLBI_VAALE1OS, HFGITR, TLBIVAALE1OS, 1),
> + SR_FGT(OP_TLBI_VALE1OS, HFGITR, TLBIVALE1OS, 1),
> + SR_FGT(OP_TLBI_VAAE1OS, HFGITR, TLBIVAAE1OS, 1),
> + SR_FGT(OP_TLBI_ASIDE1OS, HFGITR, TLBIASIDE1OS, 1),
> + SR_FGT(OP_TLBI_VAE1OS, HFGITR, TLBIVAE1OS, 1),
> + SR_FGT(OP_TLBI_VMALLE1OS, HFGITR, TLBIVMALLE1OS, 1),
> + /* FIXME: nXS variants must be checked against HCRX_EL2.FGTnXS */
> + SR_FGT(OP_TLBI_VAALE1NXS, HFGITR, TLBIVAALE1, 1),
> + SR_FGT(OP_TLBI_VALE1NXS, HFGITR, TLBIVALE1, 1),
> + SR_FGT(OP_TLBI_VAAE1NXS, HFGITR, TLBIVAAE1, 1),
> + SR_FGT(OP_TLBI_ASIDE1NXS, HFGITR, TLBIASIDE1, 1),
> + SR_FGT(OP_TLBI_VAE1NXS, HFGITR, TLBIVAE1, 1),
> + SR_FGT(OP_TLBI_VMALLE1NXS, HFGITR, TLBIVMALLE1, 1),
> + SR_FGT(OP_TLBI_RVAALE1NXS, HFGITR, TLBIRVAALE1, 1),
> + SR_FGT(OP_TLBI_RVALE1NXS, HFGITR, TLBIRVALE1, 1),
> + SR_FGT(OP_TLBI_RVAAE1NXS, HFGITR, TLBIRVAAE1, 1),
> + SR_FGT(OP_TLBI_RVAE1NXS, HFGITR, TLBIRVAE1, 1),
> + SR_FGT(OP_TLBI_RVAALE1ISNXS, HFGITR, TLBIRVAALE1IS, 1),
> + SR_FGT(OP_TLBI_RVALE1ISNXS, HFGITR, TLBIRVALE1IS, 1),
> + SR_FGT(OP_TLBI_RVAAE1ISNXS, HFGITR, TLBIRVAAE1IS, 1),
> + SR_FGT(OP_TLBI_RVAE1ISNXS, HFGITR, TLBIRVAE1IS, 1),
> + SR_FGT(OP_TLBI_VAALE1ISNXS, HFGITR, TLBIVAALE1IS, 1),
> + SR_FGT(OP_TLBI_VALE1ISNXS, HFGITR, TLBIVALE1IS, 1),
> + SR_FGT(OP_TLBI_VAAE1ISNXS, HFGITR, TLBIVAAE1IS, 1),
> + SR_FGT(OP_TLBI_ASIDE1ISNXS, HFGITR, TLBIASIDE1IS, 1),
> + SR_FGT(OP_TLBI_VAE1ISNXS, HFGITR, TLBIVAE1IS, 1),
> + SR_FGT(OP_TLBI_VMALLE1ISNXS, HFGITR, TLBIVMALLE1IS, 1),
> + SR_FGT(OP_TLBI_RVAALE1OSNXS, HFGITR, TLBIRVAALE1OS, 1),
> + SR_FGT(OP_TLBI_RVALE1OSNXS, HFGITR, TLBIRVALE1OS, 1),
> + SR_FGT(OP_TLBI_RVAAE1OSNXS, HFGITR, TLBIRVAAE1OS, 1),
> + SR_FGT(OP_TLBI_RVAE1OSNXS, HFGITR, TLBIRVAE1OS, 1),
> + SR_FGT(OP_TLBI_VAALE1OSNXS, HFGITR, TLBIVAALE1OS, 1),
> + SR_FGT(OP_TLBI_VALE1OSNXS, HFGITR, TLBIVALE1OS, 1),
> + SR_FGT(OP_TLBI_VAAE1OSNXS, HFGITR, TLBIVAAE1OS, 1),
> + SR_FGT(OP_TLBI_ASIDE1OSNXS, HFGITR, TLBIASIDE1OS, 1),
> + SR_FGT(OP_TLBI_VAE1OSNXS, HFGITR, TLBIVAE1OS, 1),
> + SR_FGT(OP_TLBI_VMALLE1OSNXS, HFGITR, TLBIVMALLE1OS, 1),
> + SR_FGT(OP_AT_S1E1WP, HFGITR, ATS1E1WP, 1),
> + SR_FGT(OP_AT_S1E1RP, HFGITR, ATS1E1RP, 1),
> + SR_FGT(OP_AT_S1E0W, HFGITR, ATS1E0W, 1),
> + SR_FGT(OP_AT_S1E0R, HFGITR, ATS1E0R, 1),
> + SR_FGT(OP_AT_S1E1W, HFGITR, ATS1E1W, 1),
> + SR_FGT(OP_AT_S1E1R, HFGITR, ATS1E1R, 1),
> + SR_FGT(SYS_DC_ZVA, HFGITR, DCZVA, 1),
> + SR_FGT(SYS_DC_GVA, HFGITR, DCZVA, 1),
> + SR_FGT(SYS_DC_GZVA, HFGITR, DCZVA, 1),
> + SR_FGT(SYS_DC_CIVAC, HFGITR, DCCIVAC, 1),
> + SR_FGT(SYS_DC_CIGVAC, HFGITR, DCCIVAC, 1),
> + SR_FGT(SYS_DC_CIGDVAC, HFGITR, DCCIVAC, 1),
> + SR_FGT(SYS_DC_CVADP, HFGITR, DCCVADP, 1),
> + SR_FGT(SYS_DC_CGVADP, HFGITR, DCCVADP, 1),
> + SR_FGT(SYS_DC_CGDVADP, HFGITR, DCCVADP, 1),
> + SR_FGT(SYS_DC_CVAP, HFGITR, DCCVAP, 1),
> + SR_FGT(SYS_DC_CGVAP, HFGITR, DCCVAP, 1),
> + SR_FGT(SYS_DC_CGDVAP, HFGITR, DCCVAP, 1),
> + SR_FGT(SYS_DC_CVAU, HFGITR, DCCVAU, 1),
> + SR_FGT(SYS_DC_CISW, HFGITR, DCCISW, 1),
> + SR_FGT(SYS_DC_CIGSW, HFGITR, DCCISW, 1),
> + SR_FGT(SYS_DC_CIGDSW, HFGITR, DCCISW, 1),
> + SR_FGT(SYS_DC_CSW, HFGITR, DCCSW, 1),
> + SR_FGT(SYS_DC_CGSW, HFGITR, DCCSW, 1),
> + SR_FGT(SYS_DC_CGDSW, HFGITR, DCCSW, 1),
> + SR_FGT(SYS_DC_ISW, HFGITR, DCISW, 1),
> + SR_FGT(SYS_DC_IGSW, HFGITR, DCISW, 1),
> + SR_FGT(SYS_DC_IGDSW, HFGITR, DCISW, 1),
> + SR_FGT(SYS_DC_IVAC, HFGITR, DCIVAC, 1),
> + SR_FGT(SYS_DC_IGVAC, HFGITR, DCIVAC, 1),
> + SR_FGT(SYS_DC_IGDVAC, HFGITR, DCIVAC, 1),
> + SR_FGT(SYS_IC_IVAU, HFGITR, ICIVAU, 1),
> + SR_FGT(SYS_IC_IALLU, HFGITR, ICIALLU, 1),
> + SR_FGT(SYS_IC_IALLUIS, HFGITR, ICIALLUIS, 1),
> };
>
> static union trap_config get_trap_config(u32 sysreg)
> @@ -1231,6 +1336,10 @@ bool __check_nv_sr_forward(struct kvm_vcpu *vcpu)
> val = sanitised_sys_reg(vcpu, HFGWTR_EL2);
> break;
>
> + case HFGITR_GROUP:
> + val = sanitised_sys_reg(vcpu, HFGITR_EL2);
> + break;
> +
> case __NR_FGT_GROUP_IDS__:
> /* Something is really wrong, bail out */
> WARN_ONCE(1, "__NR_FGT_GROUP_IDS__");
> --
> 2.34.1
>
Reviewed-by: Jing Zhang <jingzhangos at google.com>
Jing
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