[PATCH] arm64: dts: ls1028a: add l1 and l2 cache info

[Shawn Guo]

On Mon, Jul 31, 2023 at 04:46:14PM +0800, Hui Wang wrote:
> When we ran the stress-ng cache related stressors, we got the log as
> below:
> ubuntu at ubuntu:~$ stress-ng --l1cache 4
> stress-ng: info:  [656] defaulting to a 86400 second (1 day, 0.00 secs) run per stressor
> stress-ng: info:  [656] dispatching hogs: 4 l1cache
> stress-ng: info:  [657] stress-ng-l1cache: skipping stressor, cannot determine cache level 1 information from kernel
> 
> This is because the l1 and l2 cache info is missing in the devicetree,
> ls1028a has dual cortex-a72 cores and has 48KB icache, 32KB dcache and
> 1MB l2 ucache:
>   - icache is 3-way set associative
>   - dcache is 2-way set associative
>   - l2cache is 16-way set associative
>   - line size are 64bytes
> 
> Signed-off-by: Hui Wang <hui.wang at canonical.com>

Applied, thanks!