[PATCH v2] arm64/fpsimd: Only provide the length to cpufeature for xCR registers

[Catalin Marinas]

On Mon, Jul 31, 2023 at 02:58:48PM +0100, Mark Brown wrote:
> For both SVE and SME we abuse the generic register field comparison
> support in the cpufeature code as part of our detection of unsupported
> variations in the vector lengths available to PEs, reporting the maximum
> vector lengths via ZCR_EL1.LEN and SMCR_EL1.LEN.  Since these are
> configuration registers rather than identification registers the
> assumptions the cpufeature code makes about how unknown bitfields behave
> are invalid, leading to warnings when SME features like FA64 are enabled
> and we hotplug a CPU:
> 
>   CPU features: SANITY CHECK: Unexpected variation in SYS_SMCR_EL1. Boot CPU: 0x0000000000000f, CPU3: 0x0000008000000f
>   CPU features: Unsupported CPU feature variation detected.
> 
> SVE has no controls other than the vector length so is not yet impacted
> but the same issue will apply there if any are defined.
> 
> Since the only field we are interested in having the cpufeature code
> handle is the length field and we use a custom read function to obtain
> the value we can avoid these warnings by filtering out all other bits
> when we return the register value, if we're doing that we don't need to
> bother reading the register at all and can simply use the RDVL/RDSVL
> value we were filling in instead.

Maybe that's the simplest fix, especially if you want it in stable, but
I wonder why we even bother with with treating ZCR_EL1 and SMCR_EL1 as
feature registers. We already have verify_sme_features() to check for
the mismatch. BTW, is vec_verify_vq_map() sufficient so that we can skip
the maximum vector length check?

-- 
Catalin