[PATCH 6/9] drm/bridge: synopsys: dw-mipi-dsi: Set minimum lane byte clock cycles for HSA and HBP

[neil.armstrong at linaro.org]

On 17/07/2023 08:18, Liu Ying wrote:
> According to Synopsys support channel, each region of HSA, HBP and HFP must
> have minimum number of 10 bytes where constant 4 bytes are for HSS or HSE
> and 6 bytes are for blanking packet(header + CRC).  Hence, the below table
> comes in.
> 
> +------------+----------+-------+
> | data lanes | min lbcc | bytes |
> +------------+----------+-------+
> |     1      |    10    |  1*10 |
> +------------+----------+-------+
> |     2      |    5     |  2*5  |
> +------------+----------+-------+
> |     3      |    4     |  3*4  |
> +------------+----------+-------+
> |     4      |    3     |  4*3  |
> +------------+----------+-------+
> 
> Implement the minimum lbcc numbers to make sure that the values programmed
> into DSI_VID_HSA_TIME and DSI_VID_HBP_TIME registers meet the minimum
> number requirement.  For DSI_VID_HLINE_TIME register, it seems that the
> value programmed should be based on mode->htotal as-is, instead of sum up
> HSA, HBP, HFP and HDISPLAY.
> 
> This helps the case where Raydium RM67191 DSI panel is connected, since
> it's video timing for hsync length is only 2 pixels and without this patch
> the programmed value for DSI_VID_HSA_TIME is only 2 with 4 data lanes.
> 
> Signed-off-by: Liu Ying <victor.liu at nxp.com>
> ---
>   drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c | 14 +++++++++++++-
>   1 file changed, 13 insertions(+), 1 deletion(-)
> 
> diff --git a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> index 332388fd86da..536306ccea5a 100644
> --- a/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> +++ b/drivers/gpu/drm/bridge/synopsys/dw-mipi-dsi.c
> @@ -757,12 +757,19 @@ static void dw_mipi_dsi_command_mode_config(struct dw_mipi_dsi *dsi)
>   	dsi_write(dsi, DSI_MODE_CFG, ENABLE_CMD_MODE);
>   }
>   
> +static const u32 minimum_lbccs[] = {10, 5, 4, 3};
> +
> +static inline u32 dw_mipi_dsi_get_minimum_lbcc(struct dw_mipi_dsi *dsi)
> +{
> +	return minimum_lbccs[dsi->lanes - 1];
> +}
> +
>   /* Get lane byte clock cycles. */
>   static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
>   					   const struct drm_display_mode *mode,
>   					   u32 hcomponent)
>   {
> -	u32 frac, lbcc;
> +	u32 frac, lbcc, minimum_lbcc;
>   	int bpp;
>   
>   	bpp = mipi_dsi_pixel_format_to_bpp(dsi->format);
> @@ -778,6 +785,11 @@ static u32 dw_mipi_dsi_get_hcomponent_lbcc(struct dw_mipi_dsi *dsi,
>   	if (frac)
>   		lbcc++;
>   
> +	minimum_lbcc = dw_mipi_dsi_get_minimum_lbcc(dsi);
> +
> +	if (lbcc < minimum_lbcc)
> +		lbcc = minimum_lbcc;
> +
>   	return lbcc;
>   }
>   

Reviewed-by: Neil Armstrong <neil.armstrong at linaro.org>