[PATCH] arm64: dts: microchip: add missing cache properties

[Krzysztof Kozlowski]

As all level 2 and level 3 caches are unified, add required
cache-unified and cache-level properties to fix warnings like:

  sparx5_pcb125.dtb: l2-cache0: 'cache-level' is a required property

Signed-off-by: Krzysztof Kozlowski <krzysztof.kozlowski at linaro.org>

---

Please take the patch via sub-arch SoC tree.
---
 arch/arm64/boot/dts/microchip/sparx5.dtsi | 2 ++
 1 file changed, 2 insertions(+)

diff --git a/arch/arm64/boot/dts/microchip/sparx5.dtsi b/arch/arm64/boot/dts/microchip/sparx5.dtsi
index 0367a00a269b..6f7651b06478 100644
--- a/arch/arm64/boot/dts/microchip/sparx5.dtsi
+++ b/arch/arm64/boot/dts/microchip/sparx5.dtsi
@@ -52,6 +52,8 @@ cpu1: cpu at 1 {
 		};
 		L2_0: l2-cache0 {
 			compatible = "cache";
+			cache-level = <2>;
+			cache-unified;
 		};
 	};
 
-- 
2.34.1