[PATCH v4 4/4] pwm: meson: make full use of common clock framework

[Martin Blumenstingl]

Hi Heiner,

On Sat, Apr 15, 2023 at 8:39 AM Heiner Kallweit <hkallweit1 at gmail.com> wrote:
>
> On 14.04.2023 21:39, Martin Blumenstingl wrote:
> > Hello Heiner,
> >
> > On Thu, Apr 13, 2023 at 7:55 AM Heiner Kallweit <hkallweit1 at gmail.com> wrote:
> > [...]
> >> Tested-by: Martin Blumenstingl <martin.blumenstingl at googlemail.com>
> > Unfortunately I have some bad news and I need to take back my Tested-by :-(
> > Previously my test was: cycle through all available CPU frequencies
> > while stressing the CPU.
> > My assumption was: if the system doesn't lock up everything's fine
> > because we have a high enough voltage.
> >
> > This evening however I got a memory corruption error while trying to
> > log in via UART - which I thought was strange.
> > So I connected my logic analyzer to my Odroid-C1 and did some experiments:
> >
> > period = 30518, duty cycle = 15259 (typically used for the 32kHz
> > output to the SDIO wifi chip)
> > before your patches / after applying your patches:
> > PWM: duty cycle: 50.000000% / 50.000000%
> > PWM: period: 30.6 µs / 30.5 µs
> > Timing: Time: 15.292 µs (65.395 kHz) / 15.250 µs (65.574 kHz)
> > Timing: Average: 15.296 µs (65.377 kHz) / 15.264 µs (65.513 kHz)
> > driver debug messages with your patches applied:
> > fin_freq: 850000000 Hz
> > period=30518 cnt=25940
> > duty=15259 duty_cnt=12970
> >
> > Then I tried period = 12218, duty cycle = 0 (typically used for the
> > highest CPU voltage):
> > before your patches / after applying your patches:
> > PWM: duty cycle: 0.338983% / n/a (constant low output)
> > PWM: period: 12.3 µs / n/a
> > Timing: Time: 12.250 µs (81.633 kHz) / n/a
> > Timing: Average: 6.148 µs (162.668 kHz) / n/a
> > driver debug messages with your patches applied:
> > fin_freq: 850000000 Hz
> > period=12218 cnt=10385
> >
> With a 850MHz input clock we should see a 0.01% duty cycle with 1.2ns
> clock pulses. Can we rule out an issue with the measuring equipment?
> Is your logic analyzer able to display such short clock pulses?
Oh, you're right: my logic analyzer maxes out at 24MHz (~42ns).
So we can ignore this case.

> > Finally I tried period = 12218, duty cycle = 12218 (typically used for
> > the lowest CPU voltage):
> > before your patches / after applying your patches:
> > PWM: duty cycle: 99.661017% / n/a (constant low output)
I have to correct myself: for this case my logic analyzer sees a:
constant high signal

> > PWM: period: 12.3 µs / n/a
> > Timing: Time: 12.250 µs (81.633 kHz) / n/a
> > Timing: Average: 6.148 µs (162.668 kHz) / n/a
> > driver debug messages with your patches applied:
> > fin_freq: 850000000 Hz
> > period=12218 cnt=10385
> >
> Here I have no idea yet.
[...]
> At first I'd like to verify that the registers have the expected values.
> Can you provide the values of PWM_A/B (depending on which channel is used in your
> case) and PWM_MISC_AB at the end of meson_pwm_enable()? Thanks!
I'm testing with PWM_B and I get:
  REG_MISC_AB = 0x008000c2, channel reg = 0x28910000

This register value looks correct to me.

This is now my last line in meson_pwm_enable() in case you want to
sanity-check what I did:
dev_err(meson->chip.dev, "REG_MISC_AB = 0x%08x, channel reg = 0x%08x",
value, readl(meson->base + channel_data->reg_offset));


Best regards,
Martin